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부품번호 | V61C51161024 기능 |
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기능 | 64K x 16 HIGH SPEED STATIC RAM | ||
제조업체 | Mosel Vitelic Corp | ||
로고 | |||
MOSEL VITELIC
V61C51161024
64K x 16 HIGH SPEED
STATIC RAM
PRELIMINARY
Features
s High-speed: 10, 12, 15 ns
s All inputs and outputs directly TTL compatible
s Three state outputs
s Byte Control Pins
s Single 5V ± 10% Power Supply
s Packages
– 44-pin TSOP (Standard)
– 44-pin 400 mil SOJ
Description
The V61C51161024 is a 1,048,576-bit static
random-access memory organized as 65,536
words by 16 bits. Inputs and three-state outputs are
TTL compatible and allow for direct interfacing with
common system bus structures.
Functional Block Diagram
A1 VCC
Row
Memory Array
GND
A7 Decoder
A8
A9
I/O0
I/O15
UBE
LBE
OE
WE
CE
Input
Data
Circuit
Column I/O
Column Decoder
Control
Circuit
A0 A10
A15
6151161024-01
Device Usage Chart
Operating
Temperature
Range
0°C to 70 °C
V61C51161024 Rev. 1.0 July 1998
Package Outline
TK
••
Access Time (ns)
10 12 15
•••
1
Temperature
Mark
Blank
MOSEL VITELIC
V61C51161024
DC Electrical Characteristics (over all temperature ranges, VCC = 5V ± 10%)
-10 -12 -15
Symbol Parameter
Test Conditions
Min. Max. Min. Max. Min. Max. Units
IIL Input Leakage Current
IOL Output Leakage Current
ICC Operating Power Supply
Current
VCC = MAX, VIN = GND to VCC
CE = VIH, VCC = Max,
VOUT = GND to VCC
CE = VIL, IOUT = 0, f = fmax
— 5 — 5 — 5 mA
— 5 — 5 — 5 mA
— 220 — 210 — 200 mA
ISB Standby Power Supply
Current (TTL Level)
CE = VIH, f = fmax
— 60 — 50 — 40 mA
ISB1 Standby Power Supply
Current (CMOS Level)
CE ³ VCC – 0.2V, f = 0, VIN £ 0.2V — 5.0 — 5.0 — 5.0
or VIN > VCC – 0.2V
VOL Output Low Voltage
IOL = 8mA
— 0.4 — 0.4 — 0.4
VOH Output High Voltage
IOH = -4mA
2.4 — 2.4 — 2.4 —
NOTES:
1. These are absolute values with respect to device ground and all overshoots due to system or tester noise are included.
2. VIL (Min.) = -3.0V for pulse width < 20ns.
3. fMAX = 1/tRC.
4. Maximum values.
mA
V
V
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Timing Reference Levels
Output Load
0 to 3V
3 ns
1.5V
see below
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
FROM H TO L
WILL BE
CHANGING
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
CHANGING
FROM L TO H
DON'T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CHANGING:
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
“OFF” STATE
V61C51161024 Rev. 1.0 July 1998
AC Test Loads and Waveforms
+5V
480 ½
I/O Pins
255 ½
CL = 30 pF*
I/O Pins
+5V
480 ½
255 ½
CL = 5pF*
for tCLZ, tCHZ, tOLZ, tWHZ, tOW, and tOHZ
* Includes scope and jig capacitance
6151161024-05
4
4페이지 MOSEL VITELIC
Switching Waveforms (Write Cycle)
Write Cycle 1 (WE Controlled)(4)
ADDRESS
CE
WE
UBE, LBE
OUTPUT
INPUT
tAS
tWHZ(3)
tWC
tCW(6)
tAW
tBW
tWP(1)
tDW
V61C51161024
tWR(2)
tDH
51161024-10
Write Cycle 2 (CE Controlled)(4)
ADDRESS
CE
tAS
WE
UBE, LBE
tWC
tCW(6)
tAW
tBW
tWR(2)
OUTPUT
Hi-Z
INPUT
tDW tDH (5)
51161024-11
NOTES:
1. The internal write time of the memory is defined by the overlap of CE active and WE low. All signals must be active to initiate and
any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second
transition edge of the signal that terminates the write.
2. tWR is measured from the earlier of CE or WE going high.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the outputs must not be applied.
4. OE = VIL or VIH. However it is recommended to keep OE at VIH during write cycle to avoid bus contention.
5. If CE is LOW during this period, I/O pins are in the output state. Then the data input signals of opposite phase to the outputs must
not be applied to them.
6. tCW is measured from CE going low to the end of write.
V61C51161024 Rev. 1.0 July 1998
7
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
V61C51161024 | 64K x 16 HIGH SPEED STATIC RAM | Mosel Vitelic Corp |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |