V62C1161024L-85T Datasheet PDF - Mosel Vitelic Corp
| Part Number | V62C1161024L-85T | |
| Description | Ultra Low Power 64K x 16 CMOS SRAM | |
| Manufacturers | Mosel Vitelic Corp | |
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V62C1161024L(L)
Ultra Low Power
64K x 16 CMOS SRAM
Features
Functional Description
• Ultra Low-power consumption
- Active: 30mA ICC at 70ns
- Stand-by: 5 µA (CMOS input/output)
1 µA (CMOS input/output, L version)
• 70/85/100/120 ns access time
• Equal access and cycle time
• Single +1.8V to 2.2V Power Supply
• Tri-state output
• Automatic power-down when deselected
The V62C1161024L is a Low Power CMOS Static RAM
organized as 65,536 words by 16 bits. Easy memory exp-
ansion is provided by an active LOW (CE) and (OE) pin.
This device has an automatic power-down mode feature
when deselected. Separate Byte Enable controls (BLE
and BHE) allow individual bytes to be accessed. BLE
controls the lower bits I/O1 - I/O8. BHE controls the
upper bits I/O9 - I/O16.
Writing to these devices is performed by taking Chip
Enable (CE) with Write Enable (WE) and Byte Enable
(BLE/BHE) LOW.
• Multiple center power and ground pins for
improved noise immunity
• Individual byte controls for both Read and
Write cycles
Reading from the device is performed by taking Chip
Enable (CE) with Output Enable (OE) and Byte Enable
(BLE/BHE) LOW while Write Enable (WE) is held
HIGH.
• Available in 44 pin TSOP (II) Package
Logic Block Diagram
TSOP(II)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
I/O1 - I/O8
I/O9 - I/O16
WE
OE
BHE
BLE
CE
Pre-Charge Circuit
Memory Array
1024 X 1024
Vcc
Vss
Data
Cont I/O Circuit
Data
Cont
Column Select
A10 A11 A12 A13 A14 A15
A4 1
A3 2
A2 3
A1 4
A0 5
CE 6
I/O1 7
I/O2 8
I/O3 9
I/O4 10
Vcc 11
Vss 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A15 18
A14 19
A13 20
A12 21
NC 22
44 A5
43 A6
42 A7
41 OE
40 BHE
39 BLE
38 I/O16
37 I/O15
36 I/O14
35 I/O13
34 Vss
33 Vcc
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 NC
27 A8
26 A9
25 A10
24 A11
23 NC
REV. 1.1 April 2001 V62C1161024L(L)
1
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V62C1161024L(L)
Timing Waveform of Read Cycle 1 (Address Controlled)
Address
Data Out
tOH
Previous Data Valid
tRC
tAA
Timing Waveform of Read Cycle 2
Address
CE
(BLE/BHE)
OE
Data Out
High-Z
tAA
tACE
tLZ(4,5)
tBA
tBLZ(4,5)
tOE
tOLZ
tRC
Data Valid
tHZ(3,4,5)
tBHZ(3,4,5)
tOHZ
Data Valid
tOH
Notes (Read Cycle)
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to VOH or VOL levels.
4. At any given temperature and voltage condition tHZ (max.) is less than tLZ (min.) both for a given device and from device to
device.
5. Transition is measured + 200mV from steady state voltage with load. This parameter is sampled and not 100% tested.
6. Device is continuously selected with CE = VIL.
7. Address valid prior to coincident with CE transition Low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
9. For test conditions, see AC Test Condition, Figure A.
REV. 1.1 April 2001 V62C1161024L(L)
5
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for V62C1161024L-85T electronic component. |
| Information | Total 10 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ V62C1161024L-85T.PDF Datasheet ] | |
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