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부품번호 | V62C3802048LL-45V 기능 |
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기능 | Ultra Low Power 256K x 8 CMOS SRAM | ||
제조업체 | Mosel Vitelic Corp | ||
로고 | |||
V62C3802048L(L)
Ultra Low Power
256K x 8 CMOS SRAM
Features
• Low-power consumption
- Active: 40mA at 35ns
- Stand-by: 10 µA (CMOS input/output)
2 µA CMOS input/output, L version
• Single + 2.7 to 3.3V Power Supply
• Equal access and cycle time
• 35/45/55/70/85/100 ns access time
• Easy memory expansion with CE1, CE2
and OE inputs
• 1.0V data retention mode
• TTL compatible, Tri-state input/output
• Automatic power-down when deselected
• Package available: 32-TSOP1 / STSOP
• 48 Ball CSP_BGA
Functional Description
The V62C3802048L is a low power CMOS Static RAM orga-
nized as 262,144 words by 8 bits. Easy memory expansion is p-
rovided by an active LOW CE1, an active HIGH CE2, an acti-
ve LOW OE , and Tri-state I/O’s. This device has an autom-
atic power-down mode feature when deselected.
Writing to the device is accomplished by taking Chip En-
able 1 (CE1) with Write Enable (WE ) LOW, and Chip Enab-
le 2 (CE2) HIGH. Reading from the device is performed by
taking Chip Enable 1 (CE1) with Output Enable (OE)
LOW while Write Enable (WE ) and Chip Enable 2 (CE2)
is HIGH. The I/O pins are placed in a high-impedance sta-
te when the device is deselected: the outputs are disabled d-
uring a write cycle.
The V62C3802048LL comes with a 1V data retention feature
and Lower Standby Power. The V62C3802048L is available in
a 32-pin 8 x 20 mm TSOP1/8 x 13.4mm STSOP and CSP type
48-fpBGA packages.
Logic Block Diagram
32-Pin TSOP1 / STSOP(CSP_BGA see next page)
INPUT BUFFER
A0
A1
A2
A3
A4
A5 Cell Array
A6
A7
A8
A9
COLUMN DECODER
A10 A11 A12 A13 A14 A15 A16 A17
I/O8
I/O1
CONTROL
CIRCUIT
OE
WE
CE1
CE2
A11
A9
A8
A13
WE
CE2
A15
Vcc
A17
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REV. 1.2 May 2001 V62C3802048L(L)
1
32 OE
31 A10
30 CE1
29 I/O8
28 I/O7
27 I/O6
26 I/O5
25 I/O4
24 GND
23 I/O3
22 I/O2
21 I/O1
20 A0
19 A1
18 A2
17 A3
V62C3802048L(L)
DC Operating Characteristics (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = 00C to +700C / -400C to 850C)
Parameter
Input Leakage Current
Sym Test Conditions
IILII
Vcc = Max,
Vin = Gnd to Vcc
-55 -70 -85 -100
Unit
Min Max Min Max Min Max Min Max
- 1 - 1 - 1 - 1 µA
Output Leakage
Current
IILOI
CE1 = VIH or CE2 = VIL
Vcc= Max, VOUT = Gnd to Vcc
-
1
-
1
-
1
-
1 µA
Operating Power
Supply Current
ICC CE1 = VIL , CE2 = VIH
VIN = VIHor VIL ,IOUT=0mA
- 3 - 3 - 3 - 3 mA
Average Operating
Current
ICC1 CE1 = VIL , CE2 = VIH
IOUT = 0mA,
Min Cycle, 100% Duty
- 35 - 35 - 30 - 25 mA
ICC2 CE1 = 0.2V ,
CE2 =Vcc - 0.2V
IOUT = 0mA,
Cycle Time=1µs, 100% Duty
- 3 - 3 - 3 - 3 mA
Standby Power Supply ISB CE1 = VIH or CE2 = VIL
Current (TTL Level)
- 0.5 - 0.5 - 0.5 - 0.5 mA
Standby Power Supply ISB1 CE1 > Vcc - 0.2V or
Current (CMOS Level)
CE2 < 0.2V, f = 0
VIN < 0.2V or
VIN > Vcc- 0.2V
- 10 - 10 - 10 - 10 µA
L - 2 - 2 - 2 - 2 µA
Output Low Voltage
VOL IOL = 2 mA
- 0.4 - 0.4 - 0.4 - 0.4 V
Output High Voltage
VOH IOH = -2 mA
2.4 - 2.4 - 2.4 - 2.4 -
V
Capacitance (f = 1MHz, TA = 250C)
Parameter*
Symbol
Input Capacitance
Cin
I/O Capacitance
CI/O
* This parameter is guaranteed by device characterization and is not production tested.
Test Condition
Vin = 0V
Vin = Vout = 0V
Max
7
8
Unit
pF
pF
AC Test Conditions
Input Pulse Level
0.6V to 2.2V
Input Rise and Fall Time
5ns
Input and Output Timing
Reference Level
50% of input level
(VIL+VIH)/2
Output Load Condition
70ns/85 ns
Load 100ns/120 ns
CL = 30pf + 1TTL Load
CL = 100pf + 1TTL Load
CL*
Figure A.
* Including Scope and Jig Capacitance
REV. 1.2 May 2001 V62C3802048L(L)
4
4페이지 V62C3802048L(L)
Read Cycle (3,9) (Vcc = 2.7 to3.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Symbol -35
-45 Unit Note
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Output Hold fromAddress Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Power-Up Time
Power-Down Time
Min Max Min Max
tRC
35 - 45 -
ns
tAA - 35 - 45 ns
tACE - 35 - 45 ns
tOE - 20 - 20 ns
tOH
5-5-
ns
tCLZ
5-5-
ns 4,5
tCHZ - 20 - 25 ns 4,5
tOLZ
5-5-
ns 4,5
tOHZ - 15 - 20 ns 4,5
tPU 0 - 0 - ns 5
tPD
- 35 - 45 ns
5
Write Cycle (3,11) (Vcc = 2.7 to 3.3V, Gnd = 0V, TA = 00C to +700C / -400C to +850C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovering Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
Symbol -35
-45 Unit
Min Max Min Max
tWC
35 - 45 -
ns
tCW
30 - 40 -
ns
tAW
30 - 40 -
ns
tAS
0-0-
ns
tWP
30 - 35 -
ns
tWR
0-0-
ns
tDW
20 - 25 -
ns
tDH
0-0-
ns
tWZ - 20 - 25 ns
tOW
5-5-
ns
Note
4,5
4,5
REV. 1.2 May 2001 V62C3802048L(L)
7
7페이지 | |||
구 성 | 총 12 페이지수 | ||
다운로드 | [ V62C3802048LL-45V.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
V62C3802048LL-45B | Ultra Low Power 256K x 8 CMOS SRAM | Mosel Vitelic Corp |
V62C3802048LL-45T | Ultra Low Power 256K x 8 CMOS SRAM | Mosel Vitelic Corp |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |