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VC162373ADL 데이터시트 PDF




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부품번호 VC162373ADL 기능
기능 16-bit D-type transparent latch with 30 ohm series termination resistors; 5 V input/output tolerant; 3-state
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VC162373ADL 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
DATA SHEET
74LVC162373A; 74LVCH162373A
16-bit D-type transparent latch with
30 series termination resistors;
5 V input/output tolerant; 3-state
Product specification
File under Integrated Circuits, IC24
1999 Aug 05




VC162373ADL pdf, 반도체, 판매, 대치품
Philips Semiconductors
16-bit D-type transparent latch with 30 series
termination resistors; 5 V input/output tolerant; 3-state
Product specification
74LVC162373A;
74LVCH162373A
handbook, halfpage
1OE 1
48 1LE
1Q0 2
1Q1 3
47 1D0
46 1D1
GND 4
45 GND
1Q2 5
1Q3 6
VCC 7
1Q4 8
1Q5 9
44 1D2
43 1D3
42 VCC
41 1D4
40 1D5
GND 10
39 GND
1Q6 11
1Q7 12
2Q0 13
2Q1 14
162373A
38 1D6
37 1D7
36 2D0
35 2D1
GND 15
34 GND
2Q2 16
2Q3 17
VCC 18
2Q4 19
2Q5 20
33 2D2
32 2D3
31 VCC
30 2D4
29 2D5
GND 21
28 GND
2Q6 22
2Q7 23
2OE 24
27 2D6
26 2D7
25 2LE
MNA424
handbook, halfpage
1 24
1OE 2OE
47 1D0
1Q0 2
46 1D1
1Q1 3
44 1D2
1Q2 5
43 1D3
1Q3 6
41 1D4
1Q4 8
40 1D5
1Q5 9
38 1D6
1Q6 11
37 1D7
1Q7 12
36 2D0
2Q0 13
35 2D1
2Q1 14
33 2D2
2Q2 16
32 2D3
2Q3 17
30 2D4
2Q4 19
29 2D5
2Q5 20
27 2D6
2Q6 22
26 2D7
2Q7 23
1LE 2LE
48 25 MNA425
Fig.1 Pin configuration.
1999 Aug 05
4
Fig.2 Logic symbol.

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VC162373ADL 전자부품, 판매, 대치품
Philips Semiconductors
16-bit D-type transparent latch with 30 series
termination resistors; 5 V input/output tolerant; 3-state
Product specification
74LVC162373A;
74LVCH162373A
DC CHARACTERISTICS
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
OTHER
VCC (V)
40 to +85
UNIT
MIN. TYP.(1) MAX.
VIH HIGH-level input voltage
VIL LOW-level input voltage
1.2 VCC
2.7 to 3.6 2.0
1.2
2.7 to 3.6
−−V
−−
GND V
0.8
VOH
VOL
II
IOZ
Ioff
ICC
ICC
HIGH-level output voltage
LOW-level output voltage
input leakage current
3-state output OFF-state
current
power off leakage supply
quiescent supply current
additional quiescent
supply current per control
pin
VI = VIH or VIL; IO = 6 mA
VI = VIH or VIL;
IO = 100 µA
VI = VIH or VIL; IO = 12 mA
VI = VIH or VIL; IO = 6 mA
VI = VIH or VIL; IO = 100 µA
VI = VIH or VIL; IO = 12 mA
VI = 5.5 V or GND; note 2
VI = VIH or VIL;
VO = 5.5 V or GND
VI or VO = 5.5 V
VI = VCC or GND; IO = 0
VI = VCC 0.6 V; IO = 0
2.7
3.0
3.0
2.7
3.0
3.0
3.6
3.6
0.0
3.6
2.7 to 3.6
VCC 0.5
VCC 0.2
VCC 0.8
VCC
±0.1
0.1
0.1
0.1
5
0.40
0.20
0.55
±5
±5
±10
20
500
V
V
µA
µA
µA
µA
µA
IBHL bus hold LOW sustaining VI = 0.8 V; notes 3, 4 and 5 3.0 75
current
− − µA
IBHH bus hold HIGH sustaining VI = 2.0 V; notes 3, 4 and 5 3.0
current
75
− − µA
IBHLO
bus hold LOW overdrive VI = 0.8 V; notes 3, 4 and 6 3.6
current
500
− − µA
IBHHO
bus hold HIGH overdrive VI = 0.8 V; notes 3, 4 and 6 3.6
current
500 − − µA
Notes
1. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
2. For bus hold parts, the bus hold circuit is switched off when VI exceeds VCC allowing 5.5 V on the input terminal.
3. Valid for data inputs of bus hold parts (LVCH162373-A) only.
4. For data inputs only, control inputs do not have a bus hold circuit.
5. The specified sustaining current at the data input holds the input below the specified VI level.
6. The specified overdrive current at the data input forces the data input to the opposite logic input state.
1999 Aug 05
7

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