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PDF VES1820X Data sheet ( Hoja de datos )
| Número de pieza | VES1820X | |
| Descripción | SINGLE CHIP DVB-C CHANNEL RECEIVER | |
| Fabricantes | NXP Semiconductors | |
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Hay una vista previa y un enlace de descarga de VES1820X (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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VES1820X
SINGLE CHIP
DVB-C
CHANNEL RECEIVER
FEATURES
• 16/32/64/128/256 QAM demodulator
(DVB-C compatible : ETS 300-429).
• On chip 9-bit ADC.
• On chip PLL for crystal frequency
multiplication.
• Digital down conversion.
• Half Nyquist filters (roll off = 15 %).
• Automatic gain control PWM output
(AGC).
• Symbol timing recovery, with
programmable second order loop filter.
• Variable symbol rate capability from
SACLK/64 to SACLK/4
(SACLK max = 36 MHz)
• Programmable anti-aliasing filters.
• Full digital carrier recovery loop.
• Carrier acquisition range up to 8 % of
symbol rate.
• Integrated adaptative equalizer (Linear
Transversal Equalizer or Decision
Feedback Equalizer).
• On chip FEC decoder (Deinterleaver &
RS decoder), full DVB-C compliant.
• DVB compatible differential decoding
and mapping.
• Parallel or serial transport stream
interface.
• I2C bus interface, for easy control.
• CMOS 0.35µm technology.
APPLICATIONS
• DVB-C fully compatible.
• Digital data transmission using QAM modulations.
• Cable demodulation.
• Cable modems
• MMDS (ETS 300-429).
DESCRIPTION
The VES1820X is a single chip channel receiver for 16, 32, 64, 128
and 256-QAM modulated signals. The device interfaces directly to
the IF signal, which is sampled by a 9-bit AD converter.
The VES1820X performs the clock and the carrier recovery
functions. The digital loop filters for both clock and carrier recovery
are programmable in order to optimize their characteristics
according to the current application.
After base band conversion, equalization filters are used for echo
cancellation in cable applications. These filters are configured as T-
spaced transversal equalizer or DFE equalizer, so that the system
performance can be optimized according to the network
characteristics. A proprietary equalization algorithm, independent of
carrier offset, is achieved in order to assist carrier recovery. Then a
decision directed algorithm takes place, to achieve final
equalization convergence.
The VES1820X implements a FORNEY convolutional deinterleaver
of depth 12 blocks and a Reed-Solomon decoder which corrects up
to 8 erroneous bytes. The deinterleaver and the RS decoder are
automatically synchronized thanks to the frame synchronization
algorithm which uses the MPEG2 sync byte. Finally descrambling
according to DVB-C standard, is achieved at the Reed Solomon
output. This device is controlled via an I2C bus.
Designed in 0.35 µm CMOS technology and housed in a 100 pin
MQFP package, the VES1820X operates over the commercial
temperature range.
comatlas S.A., 30 rue du Chêne Germain, BP 814, 35518 CESSON-SEVIGNE Cedex, FRANCE
Phone : +33 (0)2 99 27 55 55, Fax : +33 (0)2 99 27 55 27 , Internet: www.comatlas.fr / VES 1820X rev 2.0 / Mar 99
1 page  
FUNCTIONAL DESCRIPTION
½ ADC
The VES1820X implements a 9-bit analog to digital converter. No external voltage references are required to use
the ADC.
½ PLL
The VES1820X implements a PLL used as clock multiplier by 1, 2, 3, 4, 5, 6, 7 or 8, so that the crystal can be
low frequency (fundamental tone).
½ DOWN CONVERTER AND NYQUIST FILTERS
The digital down converter performs the down conversion of the bandpass input signal into the 2 classical
quadrature I & Q channels. Then these two signals are passed through anti-alias filters and through a half
Nyquist filter having a fixed roll-off of 0.15. The digital filter gives a stop band attenuation of more than 40 dB.
½ EQUALIZER
After Nyquist filtering, the signal is fed to an equalization filter, for echo cancellation. This equalizer can be
configured as either a transversal Equalizer or a decision feedback equalizer. The following table shows some
-4
echos configuration that the VES1820X corrects with an equivalent degradation of less than 1dB @ BER = 10 .
DELAY
(nS)
50
150
and
800
1600
AMPLITUDE
(dB)
-10
-12
and
-20
-20
PHASE
worst
worst
worst
½ CARRIER RECOVERY
The carrier synchronizer implements a fully digital algorithm allowing to recover carrier frequency offsets up to
± 8 % symbol rate. A phase error detector followed by a programmable second order loop filter provides an
estimation of the carrier phase, to compensate the input carrier frequency offset.
½ CLOCK RECOVERY
A timing error detector implements an application of Gardner algorithm for digital clock recovery.
The resulting error is fed to a programmable second order loop filter, which provides a 8-bit command to the
NCO block. This one allows to determine the right sampling time instant of the input signal.
½ AUTOMATIC GAIN CONTROL
An estimation of input signal magnitude is performed and compared to a threshold value which is programmable
via the microcontroller interface. The resulting error is then filtered to produce an 10-bit command which is then
PWM encoded and provided on pin VAGC. The PWM signal can be passed through a single RC filter to control
the input gain amplifier.
½ OUTPUT INTERFACE
After carrier recovery, the demodulated output symbol must be decoded according to the constellation diagram
given by DVB standard for 16, 32, 64, 128 and 256 QAM. The resulting symbols are then differentially decoded
(DVB compliant) and serially provided to the FEC part.
½ BLOCK SYNCHRONIZATION
At demodulator output, the length of some error bursts may exceed that which can be reliably corrected by the
Reed-Solomon decoder. The implemented de-interleaving is a convolutional one (Forney) of depth 12. The first
operation consists in synchronizing the de-interleaver. This is accomplished by detecting α consecutive MPEG2
sync words (or sync ) which are present as the first byte of each packet.
comatlas reserves the right to make any change at anytime without notice.
VES 1820X rev 2.0 / Mar 99 / p5
5 Page 
TABLE 3 : PIN DESCRIPTION
Pin Pin Name Direction
1 VDD
-
2 XIN
I
3 XOUT
O
4 GND
-
5 FI[8]
I
6 FI[7]
I
7 FI[6]
I
8 FI[5]
I
9 VDD
-
10 GND
-
11 GND
-
12 FI[4]
I
13 FI[3]
I
14 FI[2]
I
15 FI[1]
I
16 FI[0]
I
17 VCC
-
18 SACLK
O
19 TEST
I
20 VAGC
O
21 IICDIV[1]
I
22 IICDIV[1]
I
23 SADDR[1]
I
24 SADDR[0]
I
25 SCL
I
26 SDA
I/O
27 CLR#
I
28 VDD
-
29 GND
-
30 GND
-
31 CTRL1
I/O
32 CTRL2
OD
33 TCK
I
Pin Pin Name Direction
34 TDI
I
35 TRST
I
36 TMS
I
37 TDO
OD
38 IT
OD
39 FEL
OD
40 VDD
-
41 GND
-
42 UNCOR
O
43 PSYNC
O
44 OCLK
O
45 DEN
O
46 DO[7]
O
47 VDD
-
48 GND
-
49 DO[6]
O
50 DO[5]
O
51 DO[4]
O
52 DO[3]
O
53 DO[2]
O
54 DO[1]
O
55 DO[0]
O
56 TESTO[0]
O
57 TESTO[1]
O
58 VDD
-
59 GND
-
60 TESTO[2]
O
61 TESTO[3]
O
62 TESTO[4]
O
63 TESTO[5]
O
64 TESTO[6]
O
65 VDD
-
66 GND
-
Pin Pin Name Direction
67 TESTO[7]
O
68 TESTO[8]
O
69 TESTO[9]
O
70 TESTO[10]
O
71 TESTO[11]
O
72 VDD
-
73 GND
-
74 TESTO[12]
O
75 TESTO[13]
O
76 TESTO[14]
O
77 TESTO[15]
O
78 TESTO[16]
O
79 VS4
-
80 VS1
-
81 VD1
-
82 RBIAS
I
83 CMI
O
84 CMO
O
85 CMCAP
I
86 VREFM
O
87 VREFP
O
88 VREF
O
89 VD3
-
90 VS3
-
91 VIM
I
92 VIP
I
93 VS2
-
94 VD2
-
95 VD4
-
96 DVCC
-
97 DGND
-
98 PLLGND
-
99 PLLVCC
-
100 PPLUS
-
Notes :
1.All inputs (I) are TTL, 5V tolerant inputs
2.OD are Open Drain 5V outputs, so they must be connected to a pull-up resistor to either VDD or VCC
comatlas reserves the right to make any change at anytime without notice.
VES 1820X rev 2.0 / Mar 99 / p11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet VES1820X.PDF ] | |
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