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VFC100AG 데이터시트 PDF




Burr-Brown Corporation에서 제조한 전자 부품 VFC100AG은 전자 산업 및 응용 분야에서
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부품번호 VFC100AG 기능
기능 Synchronized VOLTAGE-TO-FREQUENCY CONVERTER
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VFC100AG 데이터시트, 핀배열, 회로
® VFC100
FPO
Synchronized
VOLTAGE-TO-FREQUENCY CONVERTER
FEATURES
q FULL-SCALE FREQUENCY SET BY
SYSTEM CLOCK; NO CRITICAL
EXTERNAL COMPONENTS REQUIRED
q PRECISION 10V FULL-SCALE INPUT,
0.5% max GAIN ERROR
q ACCURATE 5V REFERENCE VOLTAGE
q EXCELLENT LINEARITY:
0.02% max at 100kHz FS
0.1% max at 1MHz FS
q VERY LOW GAIN DRIFT: 50ppm/°C
APPLICATIONS
q A/D CONVERSION
q PROCESS CONTROL
q DATA ACQUISITION
q VOLTAGE ISOLATION
DESCRIPTION
The VFC100 voltage-to-frequency converter is an
important advance in VFCs. The well-proven charge
balance technique is used; however, the critical reset
integration period is derived from an external clock
frequency. The external clock accurately sets an out-
put full-scale frequency, eliminating error and drift
from the external timing components required for
other VFCs. A precision input resistor is provided
which accurately sets a 10V full-scale input voltage.
In many applications the required accuracy can be
achieved without external adjustment.
The open collector active-low output provides fast fall
time on the important leading edge of output pulses,
and interfaces easily with TTL and CMOS circuitry.
An output one-shot circuit is particularly useful to
provide optimum output pulse widths for optical cou-
plers and transformers to achieve voltage isolation. An
accurate 5V reference is also provided which is useful
for applications such as offsetting for bipolar input
voltages, exciting bridges and sensors, and autocali-
bration schemes.
VIN
Non-Inverting
Input
C INT
5
– Comparator
VOUT
Input
4 14
Clock
Input
10
7 RIN
Integrator
Amplifier
6 20k
SW1
Comparator
Clocked
Logic
+VCC
1
Output
One-Shot
11
fOUT
12 Digital
Common
1mA
–VCC
13
Analog
Common
15
+ Comparator
Input
5V
Reference
16
VREF
9
COS
8
–VCC
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1984 Burr-Brown Corporation
PDS-547H
Printed in U.S.A. June, 1995




VFC100AG pdf, 반도체, 판매, 대치품
TYPICAL PERFORMANCE CURVES
At +25°C, ±VCC = 15VDC, and in circuit of Figure 1.
QUIESCENT CURRENT vs TEMPERATURE
20
REFERENCE VOLTAGE vs REFERENCE LOAD CURRENT
5.01
15
+I CC
10
–I CC
5
5
4.99
4.98
4.97
Short Circuit
Current Limit
0
–75 –50 –25
0
25 50 75
Ambient Temperature (°C)
100 125
4.96
0
5 10 15 20 25 30
Output Current (mA)
THEORY OF OPERATION
The VFC100 monolithic voltage-to-frequency converter pro-
vides a digital pulse train output with an average frequency
proportional to the analog input voltage. The output is an
active low pulse of constant duration, with a repetition rate
determined by the input voltage. Falling edges of the output
pulses are synchronized with rising edges of the clock input.
Operation is similar to a conventional charge balance VFC.
An input operational amplifier (Figure 1) is configured as an
integrator so that a positive input voltage causes an input
current to flow in RIN. This forces the integrator output to
ramp negatively. When the output of the integrator crosses
the reference voltage (5V), the comparator trips, activating
the clocked logic circuit. Once activated, the clocked logic
awaits a falling edge of the clock input, followed by a rising
edge (see Figure 2). On the rising edge, switch S1 is closed
for one complete clock cycle, causing the reset current, I1, to
switch to the integrator input. Since I1 is larger than the input
current, IIN, the output of the integrator ramps positively
during the one clock cycle reset period. The clocked logic
circuitry also generates a VFC output pulse during the reset
period.
Unlike conventional VFC circuits, the VFC100 accurately
derives its reset period from an external clock frequency.
This eliminates the critical timing capacitor required by
other VFC circuits. One period (from rising edge to rising
edge) of the clock input determines the integrator reset
period.
When the negative-going integration of the input signal
crosses the comparator threshold, integration of the input
signal will continue until the reset period can start (awaiting
®
VFC100
4

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VFC100AG 전자부품, 판매, 대치품
CINT
5
4
7 RIN
VIN
6
Clock
+VCC = 15VDC
14 10
Clocked
Logic
1 0.1µF
+VCC
Output
One-Shot
VL
0.1µF
11 fOUT
12
–VCC
13
15
5V
Reference
16
–VCC
COS
+VCC
9
–VCC =
15VDC
8
0.1µF
Clock
f OUT
tO
Output Pulse Width Without COS
FIGURE 5. Circuit and Timing Diagram for Shortened Output Pulses.
The reference output amplifier is specifically designed for
excellent transient response, to provide precision in a noisy
1µF environment.
0.1µF OTHER INPUT VOLTAGE RANGES
0.01µF
1000pF
100pF
10pF
100ns
tO
1µs
10µs
100µs
1ms
Nominal Output Pulse Width, tO
10ms
FIGURE 6. Output One-Shot Capacitor Selection.
input signals in many other applications, such as offsetting
the input. It can source up to 10mA and sink 100µA. Heavy
loading of the reference will change the gain of the VFC and
affect the external reference voltage. For instance, a 10mA
load interacting with a 0.5typical output impedance will
change the VFC gain equation and reference voltage by 0.1%.
Figure 7 shows the reference used to offset the VFC transfer
function, to convert a –5V to +5V input to 0–500kHz output.
The circuit in Figure 8 uses the reference to excite a 300
bridge transducer. R1 provides the majority of the current to
the bridge while the VREF output supplies the balance and
accurately controls the bridge voltage. The VFC gain is
inversely proportional to the reference voltage, VREF. Since
the bridge gain is directly proportional to its excitation
voltage, the two equal and opposite effects cancel the effect
of reference voltage drift on gain.
The internal input resistor, RIN = 20k, sets a full-scale
input of 10V. Other input ranges can be created by using an
external gain set resistor connected to pin 5. Since the
excellent temperature drifts of the VFC100 are achieved by
careful matching of internal temperature coefficients, use of
an external gain set resistor will generally degrade this drift.
Using an external resistor to set the gain, the resulting gain
drift would be equal to the sum of the external resistor drift
and the specified current gain drift of the VFC100. Different
voltage input ranges are best implemented by using the
internal input resistor, RIN, in series or parallel with a high
quality external resistor, thus maintaining as much of the
precision temperature tracking as possible.
For best drift performance, the adjustment range of a fine
gain trim should be made as narrow as practical. R1 and R2
in Figure 9 allow gain adjustments over a ±1% range
(adequate to trim the 100kHz FS gain error to zero) and will
not significantly affect the drift performance of the VFC100.
R3, R4 and R5 allow trimming of the integrator amplifier
input offset voltage. The adjustment range is determined by
the ratio of R4 to R5. Accurate end-point calibration would
be performed by first adjusting the offset trim so that zero
volts input just causes all output pulses to cease. The gain
trim is then adjusted for the proper full-scale output fre-
quency with an accurate full-scale input voltage.
A different input voltage range could also be made by using
only a portion of the normal input range of the VFC. For
instance, a 2V full-scale input could be created by using the
®
7 VFC100

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부품번호상세설명 및 기능제조사
VFC100AG

Synchronized VOLTAGE-TO-FREQUENCY CONVERTER

Burr-Brown Corporation
Burr-Brown Corporation

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