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VG36128161A 데이터시트 PDF




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부품번호 VG36128161A 기능
기능 CMOS Synchronous Dynamic RAM
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VG36128161A 데이터시트, 핀배열, 회로
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Description
The device is CMOS Synchronous Dynamic RAM organized as 8,388,608 - word x 4 -bit x 4 - bank,
4,194,304 - word x 8 - bit x 4 - bank, or 2,097,152 - word x 16 - bit x 4 - bank. These various organizations
provide wide choice for different applications. It is designed with the state-of-the-art technology to meet stan-
dard PC100 or high speed PC133 requirement. Four internal independent banks greatly increase the perfor-
mance efficiency. It is packaged in JEDEC standard pinout and standard plastic 54-pin TSOP package.
Features
• Single 3.3V ( ±0.3V) power supply
• High speed clock cycle time : 7.5ns/10ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by BA0 & BA1 (Bank select)
• Each Bank can be operated simultaneously and independently
• I/O level : LVTTL compatible
• Random column access in every cycle
• x4, x8, x16 organization
• Input/Output controlled by DQM ( LDQM, UDQM )
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0154
Rev.1
Page 1




VG36128161A pdf, 반도체, 판매, 대치품
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
Absolute Maximum D.C. Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 to + 4.6
V
Supply voltage relative to Vss
VDD, VDDQ
-0.5 to + 4.6
V
Short circuit output current
IOUT
50 mA
Power dissipation
PD 1.0 W
Operating temperature
TOPT
0 to + 70
¢J
Storage temperature
TSTG
-55 to + 125
¢J
Caution: Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent
damage. The device is not meant to be operated under conditions outside the limits described in the
operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended
periods may affect device reliability.
Maximum A.C. Operating Requirements for LVTTL Compatible
Parameter
Symbol
Min
Input High Voltage
VIH 2.0
Input Low Voltage
VIL -0.3
Max
VDD + 0.3
0.8
Unit
V
V
Notes
1
2
Note: 1. Overshoot limit: VIH(max)=VDDQ +2.0V with a pulse with < 3ns
2. Undershoot limit: VIL(min)=VSSQ -2.0V with a pulse with < 3ns and -1.5v with a pulse < 5ns
Recommended DC Operating Conditions for LVTTL Compatible
Parameter
Symbol
Min
Supply Voltage
VDD, VDDQ
3.0
Input High Voltage, all inputs
VIH 2.0
Input Low Voltage, all inputs
VIL -0.3
Typ Max Unit
3.3 3.6 V
¡Ð
VDD + 0.3
V
¡Ð 0.8 V
Capacitance
(Ta=25°C, f = 1MHZ)
Parameter
Symbol
Min
Input capacitance (CLK)
C11 2.5
Input capacitance (all input pins except data
pins.)
C12
2.5
Data input/output capacitance
CI/O
4.0
Notes : 1. Capacitance measured with effective capacitance measuring method.
Max
4
5
6.5
Unit Notes
pF 1
pF 1
pF 1
Document : 1G5-0154
Rev.1
Page 4

4페이지










VG36128161A 전자부품, 판매, 대치품
VIS
Preliminary
VG36128401A
VG36128801A
VG36128161A
CMOS Synchronous Dynamic RAM
AC Characteristics : (Ta = 0 to 70°C V DD = 3.3V ±0.3V, VSS = 0V)
symbol
A.C. Parameter
tRC
tRCD
tRP
tRRD
tRAS
tCK2
tCK3
tCH
tCL
tAC2
tAC3
tT
tCCD
tOH
tLZ
tHZ2
tHZ3
tIS
tIH
tSRX
tPDE
tRSC
tDPL
tDAL2
tDAL3
tBDL
tREF
Row cycle time
RAS to CAS delay
Precharge to refresh/row activate command
Row activate to row activate delay
Row activate to precharge time
Clock cycle time
CL2
CL3
Clock high time
Clock low time
Access time from CLK
(positive edge)
CL2
CL3
Transition time of CLK (Rise and Fall)
CAS to CAS Delay time
Data output hold time
Data output low impedance
Data output high impedance
CL2
CL3
Data/Address/Control Input setup time
Data/Address/Control Input hold time
Minimum CKE ”High”for Self-Refresh exit
Power Down Exit set-up time
Mode Register Set Cycle
Data-in to precharge
Data-in to ACT (REF) Command
CL2
CL3
Last data in to burst stop
Refresh time
-75
Min.
Max.
60
20
15
15
37.5 100,000
7.5
7.5
2.25
2.25
5
5
1 10
1
2.5
0
4
4
1
0.5
1
2
2
2
2clk+tRP
2clk+tRP
1
64
-8H
Min.
Max.
70
20
20
20
50 100,000
10
10
3
3
6
6
1 10
1
3
0
6
6
2
1
1
2
2
1
1clk+tRP
1clk+tRP
1
64
unit
ns
ns
CLK
ns
CLK
ns
CLK
CLK
ns
CLK
ms
note
9
Document : 1G5-0154
Rev.1
Page 7

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