PDF VG3617161DT Data sheet ( Hoja de datos )

Número de pieza	VG3617161DT
Descripción	16Mb CMOS Synchronous Dynamic RAM
Fabricantes	Vanguard International Semiconductor
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No Preview Available ! VIS Preliminary VG3617161DT 16Mb CMOS Synchronous Dynamic RAM Description The VG3617161DT is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V power supply. This SDRAM is delicately designed with performance concern for current high-speed applica- tion. Programmable CAS Latency and Burst Length make it possible to be used in widely various domains. It is packaged by using JEDEC standard pinouts and standard plastic 50-pin TSOP II. Features • Single 3.3V +/- 0.3V power supply • Clock Frequency: 180MHz, 166MHz, 143MHz, 125MHz, 100MHz • Fully synchronous with all signals referenced to a positive clock edge • Programmable CAS Iatency (2,3) • Programmable burst length (1,2,4,8,& Full page) • Programmable wrap sequence (Sequential/Interleave) • Automatic precharge and controlled precharge • Auto refresh and self refresh modes • Dual internal banks controlled by A11(Bank select) • Simultaneous and independent two bank operation • I/O level : LVTTL interface • Random column access in every cycle • X16 organization • Byte control by LDQM and UDQM • 4096 refresh cycles/64ms • Burst termination by burst stop and precharge command Document:1G5-0160 Rev.1 Page 1 1 page VIS Preliminary VG3617161DT 16Mb CMOS Synchronous Dynamic RAM Capacitance (Ta=25°C,f=1MHZ) Parameter Input capacitance(CLK) Input capacitance(all input pins except data pins) Data input/output capacitance Symbol C11 C12 CI/O Typ 2.5 2.5 4.0 Max Unit 4 pF 5 pF 6.5 pF Recommended D.C. Operating Conditions (VDD = 3.3V ± 0.3V, Ta = 0 ~ 70°C) Description/test condition -5.5 -6 -7 -8 Unit Note Symbol Min. Max. Min. Max. Min. Max. Min. Max. Operating Current tRC ≥ tRC(min), Outputs Open Address changed once during tCK(min). Burst Length = 1 (One Bank Active) IDD1 190 185 165 145 3,4 Precharge Standby Current in non power-down mode IDD2N 95 85 75 65 tCK = tCK(min), CS ≥ VIH(min), CKE ≥ VIH (min) Input signals are changed once during 30ns. 3 Precharge Standby Current in non power-down mode IDD2NS 45 40 35 30 tCK = ∞ , CKE ≥ VIH (min), CLK ≤ VIL (max) Input signals are stable mA Precharge Standby Current in power-down mode IDD2P 4 4 4 4 tCK = tCK(min), CKE ≤ VIL (max) 3 Precharge Standby Current in power-down mode IDD2PS 3.5 3.5 3.5 3.5 tCK = ∞ , CKE ≤ VIL (max), CLK ≤ VIL (max) Active Standby Current in non power down mode CKE ≥ VIH (min), tCK = tCK(min)(Both Bank Actioe) Active Standby Current in power-down CKE ≤ VIL (max), tCK = tCK(min), CS ≥ VIH(min)(Both Bank Active) Operating Current (Page Burst, and All Bank activated) tCCD = tCCD(min), Outputs Open, Multi-bank interleave, gapless data Refresh Current tRC ≥ tRC (min) (tREF = 64ms) Self Refresh Current CKE ≤ 0.2V IDD3N IDD3P IDD4 IDD5 IDD6 85 75 65 55 6666 195 185 175 165 185 175 165 155 4444 3 4,5 3 Document:1G5-0160 Rev.1 Page 5 5 Page VIS Preliminary VG3617161DT 16Mb CMOS Synchronous Dynamic RAM 2.4 Operative Command Table Current state CS RAS CAS WE Address Idle HX X XX LH H XX LH L H BA,CA,A10 LH L L BA,CA,A10 LL H H BR,RA LL H L BA,A10 LL L HX LL L L Op-Code Row active HX X XX LH H XX LH L H BA,CA,A10 LH L L BA,CA,A10 LL H H BA,RA LL H L BA,A10 LL L HX LL L L Op-Code Read HX X XX LH H HX LH H LX Write LH LH LL LL LL LL HX L H BA,CA,A10 L L BA,CA,A10 H H BA,RA H L BA,A10 L HX L L Op-Code X XX LH H HX LH H LX LH LH LL LL LL LL L H BA,CA,A10 L L BA,CA,A10 H H BA,RA H L BA,A10 L HX L L Op-Code Command DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MPS DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS (1/3) Action Nop or Power down Nop or Power down ILLEGAL ILLEGAL Row active Nop Refresh or Self refresh Mode register access Nop Nop Begin read:Determine AP Begin write:Determine AP ILLEGAL Precharge ILLEGAL ILLEGAL Notes 2 2 3 3 4 5 5 3 6 Continue burst to end → Row active Continue burst to end → Row active Burst stop → Row active Term burst, new read:Determine AP Term burst, start write:Determine AP ILLEGAL Term burst,precharging ILLEGAL ILLEGAL 7 7,8 3 Continue burst to end → write recovering Continue burst to end → Write recovering Burst stop → Row active Term burst, start read: determine AP Term burst, new write:Determine AP ILLEGAL Term burst precharging ILLEGAL ILLEGAL 7,8 7 3 9 Document:1G5-0160 Rev.1 Page 11 11 Page

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