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부품번호 | VG36643241BT-8 기능 |
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기능 | CMOS Synchronous Dynamic RAM | ||
제조업체 | Vanguard International Semiconductor | ||
로고 | |||
VIS
Description
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 -
bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced
submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is
packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time : 8/10 for LVTTL
• High speed clock cycle time : 8/10 for SSTL - 3
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Dual Internal banks controlled by A11 (Bank select) for VG36643211(2)
• Quad Internal banks controlled by A11 & A12 (Bank select) for VG36643241(2)
• Each Banks can operate simultaneously and independently
• LVTTL compatible I/O interface for VG36643211 and VG36643241
• SSTL - 3 compatible I/O interface for VG36643212 and VG36643242
• Random column access in every cycle
• x32 organization
• Input/Output controlled by DQM0 ~ 3
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
Document : 1G5-0099
Rev.1
Page 1
VIS
Block Diagram
CLK
CKE
Clock
Generator
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
Address
CS
RAS
CAS
WE
Mode
Register
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
(Bank D)
(Bank C)
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
Data Control Circuit
DQM
DQ
Note: Bank C and Bank D are for VG36643241(2) only
Document : 1G5-0099
Rev.1
Page 4
4페이지 VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
A. C Characteristics : (Ta = 0 to 70°C VDD = 3.3V ± 0.3VSS = 0V)
Test Conditions for LVTTL Compatible :
AC input Levels (VIH/VIL)
2.0/0.8V
Input rise and fall time
1ns
Input timing reference level/
Output timing reference level
Output load condition
1.4V
50pF
AC Test Load Circuits (for LVTTL interface) :
VDDQ
VOUT
Device
Under
Test
VDDQ
Z = 50 Ω
1.4V
50 Ω
50PF
Test Conditions for SSTL - 3 Interface
Input Hihg (min)/Input low (max) Voltage VREF + 0.4V/ Input Reference Voltage
VREF - 0.4V (VREF)
Timing Reference Levels of Output Signals 0.45 x VDDQ Input Signal MAX. Slew Rate
Input Signal MAX. Peak to Peak Swing
2.0V
Output Circuit
Min. Required output pull - up under AC
test load
VTT + 0.8V Min. Required output pull -
down under AC test load
0.45 x VDDQ
1V/ns
See Figure
Below
VTT - 0.8V
AC Test Load Circuits (for SSTL - 3 interface) :
VDDQ
VREF
VDDQ
0.45 * VDDQ
VOUT
RS = 25Ohms
VTT = 0.45 * VDDQ
RT2 = 50 Ohms
Z = 50 Ohms
VIN
Device
Under
Test
RT1 = 50 Ohms
VTT = 0.45 * VDDQ
CLOAD = 30 pF
VREF = 0.45 * VDD
VSS
Document : 1G5-0099
Rev.1
Page 7
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ VG36643241BT-8.PDF 데이터시트 ] |
당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는 |
구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
VG36643241BT-10 | CMOS Synchronous Dynamic RAM | Vanguard International Semiconductor |
VG36643241BT-7 | CMOS Synchronous Dynamic RAM | Vanguard International Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |