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VG36644041DT 데이터시트 PDF




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부품번호 VG36644041DT 기능
기능 CMOS Synchronous Dynamic RAM
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VG36644041DT 데이터시트, 핀배열, 회로
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
Description
The VG36644041D, VG36648041D and VG36641641D are high-speed 67,108,864-bit synchronous
dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4 and 1,048,576 x 16 x
4 (word x bit x bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All input
and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are compatible
with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
Features
• Single 3.3V (±0.3V ) power supply
• High speed clock cycle time
-6 : 166MHz<3-3-3>, available only on 4MX16 option
-7 : 143MHz<3-3-3>, 133MHz<2-3-2>
-7L: 133MHz<3-3-3>
-8H: 100MHz<2-2-2>
• Fully synchronous operation referenced to clock rising edge
• Possible to assert random column access in every cycle
• Quad internal banks controlled by A12 & A13 (Bank Select)
• Byte control by LDQM and UDQM for VG36641641D
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• X4, X8, X16 organization
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64ms
• Burst termination by Burst stop and Precharge command
Document :1G5-0177
Rev.2
Page 1




VG36644041DT pdf, 반도체, 판매, 대치품
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
Pin Function
Symbol
CLK
CKE
/CS
/RAS, /CAS,
/WE
A0 - A13
BA0,BA1
DQM, UDQM ,
LDQM
DQ0 - DQ15
VDD, VSS
VDDQ, VSSQ
Input
Function
Input Maste Clock: Other inputs signals are referenecd to the CLK rising edge
Input
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals,
device input buffers and output drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any bank).
Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the com-
mand decoder. All commands are masked when CS# is registered HIGH. CS# provides
for external bank selection on systems with multiple banks. CS# is considered part of
the command code.
Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the command being
entered.
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column
address and AUTO PRECHARGE bit for READ/WRITE commands, to select one loca-
tion out of the memory array in the respective bank.
The row address is specified by A0-A11.
The column address is specified by A0-A9 (X4) / A0-A8 (X8) / A0-A7 (X16)
Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Input
Address Inputs: Provide the row address for ACTIVE commands (row address A0-
A10), and the column address and AUTO PRECHARGE bit for READ/WRITE com-
mands (column address A0-A7 with A10 defining AUTO PRECHARGE), to select one
location out of the memory array in the respective bank.
I/O Data Input / Output: Data bus
Supply Power Supply for the memory array and peripheral circuitry
Supply Power Supply are supplied to the output buffers only
Document :1G5-0177
Rev.2
Page 4

4페이지










VG36644041DT 전자부품, 판매, 대치품
VIS
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
AC Characteristics (Ta = 0 ~ 70°C, VDD = VDDQ = 3.3 ± 0.3V , VSS = VSSQ = 0V, unless otherwise noted)
Test Conditions
AC input Levels (VIH/VIL)
Input rise and fall time
2.0 / 0.8V
1ns
Input timing reference level /
Output timing reference level
Output load condition
1.4V
50pF
Note): 1.if clock rising time is longer than 1ns, (tr/2-0.5ns) should be added to the parameter.
Output Load Conditions
VDDQ
VOUT
Device
Under
Test
VDDQ
Z = 50
50PF
Document :1G5-0177
Rev.2
Page 7

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VG36644041DT

CMOS Synchronous Dynamic RAM

Vanguard International Semiconductor
Vanguard International Semiconductor

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