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VG36648041BT-7 데이터시트 PDF




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부품번호 VG36648041BT-7 기능
기능 CMOS Synchronous Dynamic RAM
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VG36648041BT-7 데이터시트, 핀배열, 회로
VIS
Description
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 2,097,152 - word x 8-bit x 4-bank. it is
fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only
power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V ( ±0.3V) power supply
• High speed clock cycle time : 7/8ns
• Fully synchronous with all signals referenced to a positive clock edge
• Programmable CAS Iatency (2,3)
• Programmable burst length (1,2,4,8,& Full page)
• Programmable wrap sequence (Sequential/Interleave)
• Automatic precharge and controlled precharge
• Auto refresh and self refresh modes
• Quad Internal banks controlled by A12 & A13 (Bank select)
• Each Bank can operate simultaneously and independently
• LVTTL compatible I/O interface
• Random column access in every cycle
• X8 organization
• Input/Output controlled by DQM
• 4,096 refresh cycles/64ms
• Burst termination by burst stop and precharge command
• Burst read/single write option
The information shown is subject to change without notice.
Document : 1G5-0153
Rev.1
Page 1




VG36648041BT-7 pdf, 반도체, 판매, 대치품
VIS
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
Absolute Maximum D.C. Ratings
Parameter
Symbol
Value
Unit
Voltage on any pin relative to Vss
VIN, VOUT
-0.5 to + 4.6
V
Supply voltage relative to Vss
VDD, VDDQ
-0.5 to + 4.6
V
Short circuit output current
IOUT
50 mA
Power dissipation
PD 1.0 W
Operating temperature
TOPT
0 to + 70
°C
Storage temperature
TSTG
-55 to + 125
°C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
peumanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Maximum A.C. Operating Requirements for LVTTL Compatible
Parameter
Symbol
Min
Max
Input High Voltage
VIH 2.0 VDDQ + 2.0
Input Low Voltage
VIL VSSQ -2.0 0.8
Unit
V
V
Notes
2
2
Recommended DC Operating Conditions for LVTTL Compatible
Parameter
Symbol
Min
Supply Voltage
Input High Voltage, all inputs
Input Low Voltage, all inputs
VDD, VDDQ
VIH
VIL
3.0
2.0
-0.3
Typ
3.3
-
-
Max
3.6
VDD + 0.3
0.8
Unit
V
V
V
Capacitance
(Ta = 25°C, f = 1MHZ)
Parameter
Symbol Min Typ Max Unit
Input capacitance (All input pins except CLK pin)
Cin
2.5 3.75 5.0
pF
CLK pin
CCLK
2.5 3.25
Data input/output capacitance
CI/O 4.0 5.25
Notes : 1. Capacitance measured with effective capacitance measuring method.
4.0
6.5
pF
pF
2. The overshoot and undershoot voltage duration is 3ns with no input clamp diodes.
Notes
1
1
1
Document : 1G5-0153
Rev.1
Page 4

4페이지










VG36648041BT-7 전자부품, 판매, 대치품
VIS
Preliminary
VG36648041CT
CMOS Synchronous Dynamic RAM
A. C Characteristics : (Ta = 0 to 70°C VDD = 3.3V 0.3V, VSS = 0V)
Parameter
CAS
Latency
symbol
VG36648041B
-7 -8
Min Max Min Max
CLK cycle time
CLK to valid output delay
CLK high pulse width
CLK low pulse width
CKE setup time
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
Data input hold time
Output data hold time
CLK to output in low - Z
CLK to output in H - Z
3 tck3
2 tck2
3 tAc3
2 tAc2
tCH
tCL
tCKS
tCKH
tAS
tAH
tCMS
tCMH
tDS
tDH
tOH
tLZ
3 tHZ
2
78
10 10
66
66
33
33
22
11
22
11
22
11
22
11
33
00
56
66
Row active to active delay
RAS to CAS delay
Row precharge time
ROW active time
ROW cycle time
Last data in to burst stop
Data - in to ACT(REF) command
tRRD
tRCD
tRP
tRAS
tRC
tBDL
tDAL
14
20
20
40
60
1
1+ tRP
120K
16
20
20
48
68
1
1+tRP
120K
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
Data - in to precharge
Transition time
Mode reg. set cycle
Power down exit setup time
Self refresh exit time
Refresh time
tDPL
tT
tRSC
tPDE
tSRX
tREF
1
1 10
2
2
1
64
1 CLK
1 10 ns
2 CLK
2 ns
1 CLK
64 ms
Document : 1G5-0153
Rev.1
Page 7

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