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기능 262/144x32x2-Bit CMOS Synchronous Graphic RAM
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VG4616322BQ-7R 데이터시트, 핀배열, 회로
VIS
Overview
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
The VG4616321(2) SGRAM is a high-speed CMOS synchronous graphics RAM containing 16M bits. It
is internally configured as a dual 256K x 32 DRAM with a synchronous interface (all signals are registered on
the positive edge of the clock signal, CLK). Each of the 256K x 32 bit banks is organized as 1024 rows by
256 columns by 32 bits. Read and write accesses to the SGRAM are burst oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed sequence. Accesses
begin with the registration of a BankActivate command which is then followed by a Read or Write command.
The VG4616321(2) provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page,
with burst termination option. An Auto Precharge function may be enabled to provide a self-timed row pre-
charge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh
are easy to use. In addition, it features the write per bit and the masked block write functions.
By having a programmable Mode register and special mode register, the system can choose the best
suitable modes to maximize its performance. These devices are well suited for applications requiring high
memory bandwidth, and when combined with special graphics functions result in a device particularly well
suited to high performance graphics applications.
Features
• Fast access time from clock: 4.5/5/5.5ns
• Fast clock rate: 200/166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• Dual internal banks(256K x 32-bit x 2-bank)
• Programmable Mode and Special Mode registers
- CAS Latency: 1, 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst Read Single Write
- Load Color or Mask register
• Burst stop function
• Individual byte controlled by DQM0-3
• Block write and write-per-bit capability
• Auto Refresh and Self Refresh
• 2048 refresh cycles/32ms
• Single + 3.3V ±0.3V power supply
• Input Reference Voltage : Vref = 1.5V ± 0.2V
• Interface: LVTTL and SSTL_3
• JEDEC 100-pin Plastic QFP package
Document:1G5-0145
Rev.1
Page 1




VG4616322BQ-7R pdf, 반도체, 판매, 대치품
VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Table 1 shows the details for pin number, symbol, type, and description.
Table 1. Pin Description of VG4616321
Pin Num- Symbol
ber
55 CLK
54 CKE
29 BS
30-34, A0-A9
47-51
28 CS
27 RAS
26 CAS
25 WE
53 DSF
Type Description
Input Clock: CLK is driven by the system clock. All SGRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and con-
trol the output registers.
Input
Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE
goes low synchronously with clock (set-up and hold time same as other inputs), the
internal clock is suspended from the next clock cycle and the state of output and
burst address is frozen as long as the CKE remains low. When both banks are in
the idle state, deactivating the clock controls the entry to the Power Down and Self
Refresh modes. CKE is synchronous except after the device enters Power Down
and Self Refresh modes, where CKE becomes asynchronous until after exiting the
same mode. The input buffers, including CLK, are disabled during Power Down
and Self Refresh modes providing low standby power.
Input Bank Select: BS defines to which bank the BankActivate, Read, Write, or Bank-
Precharge command is being applied. BS is also used to program the 10th bit of
the Mode and Special Mode registers.
Input
Address Inputs: A0-A9 are sampled during the BankActivate command (row
address A0-A9) and Read/Write command (column address A0-A7 with A9 defin-
ing Auto Precharge) to select one location out of the 256K available in the respec-
tive bank. During a Precharge command, A9 is sampled to determine if both banks
are to be precharged (A9 = HIGH). The address inputs also provide the op-code
during a Mode Register Set or Special Mode Register Set command.
Input
Chip Select: CS enables (sampled LOW) and disables (sampled HIGH) the com-
mand decoder. All commands are masked when CS is sampled HIGH. CS provides
for external bank selection on systems with multiple banks. It is considered part of
the command code.
Input
Row Address Strobe: The RAS signal defines the operation commands in con-
junction with the CAS and WE signals, and is latched at the positive edges of CLK.
When RAS and CS are asserted “LOW” and CAS is asserted “HIGH”, either the
BankActivate command or the Precharge command is selected by the WE signal.
When the WE is asserted “HIGH” the BankActivate command is selected and the
bank designated by BS is turned on to the active state. When the WE is asserted
"LOW", the Precharge command is selected and the bank designated by BS is
switched to the idle state after precharge operation.
Input
Column Address Strobe: The CAS signal defines the operation commands in
conjunction with the RAS and WE signals, and it is latched at the positive edges of
CLK. When RAS is held “HIGH” and CS is asserted “LOW”, the column access is
started by asserting CAS “LOW”. Then, the Read or Write command is selected by
asserting WE “LOW” or “HIGH”.
Input
Write Enable: The WE signal defines the operation commands in conjunction with
the RAS and CAS signals, and it is latched at the positive edges of CLK. The WE
input is used to select the BankActivate or Precharge command and Read or Write
command.
Input
Define Special Function: The DSF signal defines the operation commands in
conjunction with the RAS and CAS and WE signals, and it is latched at the positive
edges of CLK. The DSF input is used to select the masked write disable/enable
command and block write command, and the Special Mode Register Set cycle.
Document:1G5-0145
Rev.1
Page 4

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VG4616322BQ-7R 전자부품, 판매, 대치품
VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Commands
1 BankActivate & Masked Write Disable command
(RAS = ”L”, CAS = ”H”, WE = ”H”, DSF = ”L”, BS = Bank, A0-A9 = Row Address)
The BankActivate command activates the idle bank designated by the BS (Bank Select) signal. By
latching the row address on A0 to A9 at the time of this command, the selected row access is initiated.
The read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of
bank activation. A subsequent BankActivate command to a different row in the same bank can only be
issued after the previous active row has been precharged (refer to the following figure). The minimum
time interval between successive BankActivate commands to the same bank is defined by tRC(min.).
The SGRAM has two internal banks on the same chip and shares part of the internal circuitry to reduce
chip area, therefore it restricts the back-to-back activation of both banks. tRRD(min.) specifies the mini-
mum time required between activating different banks. After this command is used, the Write command
and the Block Write command perform the no mask write operation.
T0 T1 T2 T3
Tn+3
Tn+4
Tn+5
Tn+6
CLK
ADDRESS
Bank A
Row Addr.
Bank A
Col Addr.
Bank A
Row Addr.
COMMAND
RAS-CAS delay (tRCD)
Bank A
Activate
NOP
NOP
R/W A with
AutoPrecharge
RAS-RAS delay time (tRRD)
Bank B
Activate
NOP
NOP
RAS Cycle time (tRC)
: “H” or “L”
AutoPrecharge
Begin
BankActivate Command Cycle (Burst Length = n, CAS Latency = 3)
Bank A
Row Addr.
Bank A
Activate
2 BankActivate & Masked Write Enable command (refer to the above figure)
(RAS = ”L”, CAS = ”H”, WE = ”H”, DSF = ”H”, BS = Bank, A0-A9 = Row Address)
The BankActivate command activates the idle bank designated by BS signal. After this command is
performed, the Write command and the Block Write command perform the masked write operation. In
the masked write and the masked block write functions, the I/O mask data that was stored in the write
mask register is used.
3 BankPrecharge command
(RAS = ”L”, CAS = ”H”, WE = ”L”, DSF = ”L”, BS = Bank, A9 = ”L”, A0-A8 = Don’t care)
The BankPrecharge command precharges the bank designated by BS signal. The precharged
bank is switched from the active state to the idle state. This command can be asserted anytime after
tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any
bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed in
any active bank within tRAS(max.). At the end of precharge, the precharged bank is still the idle state and
ready to be activated again.
4 PrechargeAll command
(RAS = ”L”, CAS = ”H”, WE = ”L”, DSF = ”L”, BS = Don’t care, A9 = ”H”, A0-A8 = Don’t care)
The PrechargeAll command precharges both banks simultaneously. Even if both banks are not in
the active state, the PrechargeAll command can be issued. Both banks are then switched to the idle
state.
5 Read command
(RAS = ”H”, CAS = ”L”, WE = ”H”, DSF = ”L”, BS = Bank, A9 = ”L”, A0-A7 = Column Address, A8 = Don’t care)
Document:1G5-0145
Rev.1
Page 7

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부품번호상세설명 및 기능제조사
VG4616322BQ-7

262/144x32x2-Bit CMOS Synchronous Graphic RAM

Vanguard International Semiconductor
Vanguard International Semiconductor
VG4616322BQ-7R

262/144x32x2-Bit CMOS Synchronous Graphic RAM

Vanguard International Semiconductor
Vanguard International Semiconductor

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