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UT62256CPC-70LL 데이터시트 PDF




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부품번호 UT62256CPC-70LL 기능
기능 32K X 8 BIT LOW POWER CMOS SRAM
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UT62256CPC-70LL 데이터시트, 핀배열, 회로
Rev. 1.0
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
FEATURES
GENERAL DESCRIPTION
Access time : 35/70ns (max.)
Low power consumption:
Operating : 40/30 mA (typical.)
Standby : 3mA (typical) normal
2uA (typical) L-version
1uA (typical) LL-version
Single 5V power supply
All inputs and outputs are TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
Package : 28-pin 600 mil PDIP
28-pin 330 mil SOP
28-pin 8mmx13.4mm STSOP
The UT62256C is a 262,144-bit low power
CMOS static random access memory
organized as 32,768 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.
The UT62256C is designed for high-speed
and low power application. It is particularly
well suited for battery back-up nonvolatile
memory application.
The UT62256C operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible
FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATION
A4
A3
A14 .
.A13 ROW
A12 DECODER
A7
A6 .
A5
A8
I/O1
...
... I/O
CONTROL
I/O8
...
MEMORYARRAY
512 ROWS × 512 COLUMNS
. ..
COLUMNI/O
COLUMNDECODER
VCC
VSS
CE LOGIC
WE CONTROL
OE
A10 A9 A11 A2 A1 A0
PIN DESCRIPTION
SYMBOL
A0 - A14
I/O1 - I/O8
CE
WE
OE
VCC
VSS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply
Ground
OE
A11
A9
A8
A13
WE
Vcc
A14
A12
A7
A6
A5
A4
A3
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O1 11
I/O2 12
I/O3 13
Vss 14
28 Vcc
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
PDIP/SOP
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 UT62256C 21
9 20
10 19
11 18
12 17
13 16
14 15
STSOP
A10
CE
I/O8
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
A1
A2
____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1




UT62256CPC-70LL pdf, 반도체, 판매, 대치품
Rev. 1.0
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
Address
tRC
DOUT
tAA
tOH
Data Valid
tOH
READ CYCLE 2 ( CE and OE Controlled) (1,3,5,6)
Address
CE
OE
DOUT
tRC
tAA
tACE
tCLZ
High-z
tOE
tOLZ
tCHZ
tOHZ
tOH
Data valid
High-Z
Notes :
1. WE is HIGH for read cycle.
2. Device is continuously selected CE =VIL.
3. Address must be valid prior to or coincident with CE transition; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
6. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ.
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4

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UT62256CPC-70LL 전자부품, 판매, 대치품
Rev. 1.0
UTRON
UT62256C
32K X 8 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
28 pin 600 mil PDIP PACKAGE OUTLINE DIMENSION
UNIT
SYMBOL
INCH(BASE)
MM(REF)
A1 0.010 (MIN) 0.254 (MIN)
A2 0.150±0.005 3.810±0.127
B 0.020 (MAX) 0.508(MAX)
B1 0.055 (MAX) 1.397(MAX)
c 0.012 (MAX) 0.304 (MAX)
D 1.430 (MAX) 36.322 (MAX)
C E 0.6 (TYP) 15.24 (TYP)
E1 0.52 (MAX) 13.208 (MAX)
e 0.100 (TYP) 2.540(TYP)
eB 0.625 (MAX) 15.87 (MAX)
L 0.180(MAX) 4.572(MAX)
S 0.06 (MAX) 1.524 (MAX)
Q1 0.08(MAX) 2.032(MAX)
Θ
15o(MAX)
15o(MAX)
_____________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80027
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7

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