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부품번호 TSW5070FN 기능
기능 PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION
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TSW5070FN 데이터시트, 핀배열, 회로
TS5070
TS5071
PROGRAMMABLE CODEC/FILTER
COMBO 2ND GENERATION
COMPLETE CODEC AND FILTER SYSTEM
INCLUDING :
– TRANSMIT AND RECEIVE PCM CHANNEL
FILTERS
µ-LAW OR A-LAW COMPANDING CODER
AND DECODER
– RECEIVE POWER AMPLIFIER DRIVES
300
– 4.096 MHz SERIAL PCM DATA (max)
PROGRAMMABLE FUNCTIONS :
– TRANSMIT GAIN : 25.4 dB RANGE, 0.1 dB
STEPS
– RECEIVE GAIN : 25.4 dB RANGE, 0.1 dB
STEPS
– HYBRID BALANCE CANCELLATION FIL-
TER
– TIME-SLOT ASSIGNMENT: UP TO 64
SLOTS/FRAME
– 2 PORT ASSIGNMENT (TS5070)
– 6 INTERFACE LATCHES (TS5070)
– A OR µ-LAW
– ANALOG LOOPBACK
– DIGITAL LOOPBACK
DIRECT INTERFACE TO SOLID-STATE
SLICs
SIMPLIFIES TRANSFORMER SLIC, SINGLE
WINDING SECONDARY
STANDARD SERIAL CONTROL INTERFACE
80 mW OPERATING POWER (typ)
1.5mW STANDBY POWER (typ)
MEETS OR EXCEEDS ALL CCITT AND
LSSGR SPECIFICATIONS
TTL AND CMOS COMPATIBLE DIGITAL IN-
TERFACES
DESCRIPTION
The TS5070series are the second generationcom-
bined PCM CODEC and Filter devices optimized
for digital switching applications on subscriber and
trunk line cards.
Using advanced switched capacitor techniques the
TS5070 and TS5071 combine transmit bandpass
and receive lowpass channel filters with a com-
panding PCM encoder and decoder. The devices
are A-law and µ-law selectable and employ a con-
ventional serial PCM interface capable of being
clocked up to 4.096 MHz. A number of programma-
ble functions may be controlled via a serial control
port.
December 1997
DIP20 (Plastic)
ORDERING NUMBER:TS5071N
PLCC28
ORDERING NUMBERS: TS5070FN
TS5070FNTR
Channel gains are programmable over a 25.4 dB
range in each direction, and a programmable filter
is included to enable Hybrid Balancing to be ad-
justed to suit a wide range of loop impedance con-
ditions.
Both transformer and active SLIC interface circuits
with real or complex termination impedances can
be balanced by this filter, with cancellation in ex-
cess of 30 dB being readily achievable when meas-
ured across the passbandagainst standardtest ter-
mination networks.
To enable COMBO IIG to interface to the SLIC con-
trol leads, a number of programmable latches are
included ; each may be configured as either an in-
put or an output. The TS5070 provides 6 latches
and the TS5071 5 latches.
1/32




TSW5070FN pdf, 반도체, 판매, 대치품
TS5070 - TS5071
PIN CONNECTIONS
PLCC28
TS5070FN
DIP20
TS5071N
POWER SUPPLY, CLOCK
Name
Pin
Type
TS5070
FN
TS5071
N
Function
Description
VCC
S
27
19 Positive Power + 5 V ± 5 %
Supply
VSS S
3
3 Negative
–5V± 5%
Power Supply
GND
S
1
1 Ground
All analog and digital signals are referenced to this pin.
BCLK
I
16
12 Bit Clock
Bit clock input used to shift PCM data into and out of the
DR and DX pins. BCLK may vary from 64 kHz to 4.096
MHz in 8 kHz increments, and must be synchronous with
MCLK (TS5071 only).
MCLK I 17 12 Master Clock Master clock input used by the switched capacitor filters
and the encoder and decoder sequencing logic. Must be
512 kHz, 1. 536/1. 544 MHz,
2.048 MHz or 4.096 MHz and synchronous with BCLK.
BCLK and MCLK are wired together in the TS5071.
4/32

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TSW5070FN 전자부품, 판매, 대치품
POWER-DOWN STATE
Following a period of activity in the powered-up
state the power-down state may be re-entered by
writing any of the control instructions into the serial
control port with the ”P” bit set to ”1” It is recom-
mended that the chip be powered down before writ-
ing any additional instructions. In the power-down
state, all non-essential circuitry is de-activated and
the DX0 and DX1 outputs are in the high impedance
TRI-STATE condition.
The coefficients stored in the Hybrid Balance circuit
and the Gain Control registers, the data in the LDR
and ILR, and all control bits remain unchanged in
the power-down state unless changed by writing
new data via the serial control port, which remains
operational. The outputs of the Interface Latches
also remain active, maintaining the ability to moni-
tor and control a SLIC.
TRANSMIT FILTER AND ENCODER
The Transmit section input, VFXI, is a high imped-
ance summing input which is used as the differenc-
ing point for the internal hybrid balancecancellation
signal. No external components are needed to set
the gain. Following this circuit is a programmable
gain/attenuationamplifier which is controlled by the
contents of the Transmit Gain Register (see Pro-
grammable Functions section). An active prefilter
then precedes the 3rd order high-pass and 5th or-
der low-pass switched capacitor filters. The A/D
converter has a compressingcharacteristicaccord-
ing to the standard CCITT A or µ255 coding laws,
which must be selected by a controlinstructiondur-
ing initialization (see table 1 and 2). A precision on-
chip voltage reference ensures accurate and highly
stable transmission levels. Any offset voltage aris-
ing in the gain-set amplifier, the filters or the com-
parator is cancelled by an internal auto-zero circuit.
Each encode cycle begins immediately following
the assigned Transmit time-slot. The total signal
delay referenced to the start of the time-slot is ap-
proximately 165 µs (due to the Transmit Filter)
plus 125 µs (due to encoding delay), which totals
290 µs. Data is shifted out on DX0 or DX1 during
the selected time slot on eight rising edges of
BCLK.
DECODER AND RECEIVE FILTER
PCM data is shifted into the Decoder’s Receive
PCM Register via the DR0 or DR1 pin during the se-
lected time-slot on the 8 fallingedges of BCLK. The
Decoder consists of an expanding DAC with either
A or µ255 law decoding characteristic, which is se-
lected by the same control instructionused to select
the Encode law during initialization. Following the
Decoder is a 5th order low-pass switched capacitor
filter with integral Sin x/x correction for the 8 kHz
sample and hold. A programmable gain amplifier,
which must be set by writing to the Receive Gain
TS5070 - TS5071
Register,is included,and finally a Post-Filter/Power
Amplifier capable of driving a 300 load to ± 3.5
V, a 600 load to ± 3.8 V or 15 kload to ± 4.0 V
at peak overload.
A decode cycle begins immediately after each re-
ceive time-slot, and 10 µs later the Decoder DAC
output is updated. The total signal delay is 10 µs
plus 120 µs (filter delay) plus 62.5 µs (1/2 frame)
which gives approximately 190 µs.
PCM INTERFACE
The FSX and FSR frame sync inputs determine the
beginning of the 8-bit transmit and receive time-
slots respectively. They may have any duration
from a single cycle of BCLK to one MCLK period
LOW. Two different relationships may be estab-
lished betweenthe framesync inputs and theactual
time-slots on the PCM busses by setting bit 3 in the
Control Register (see table 2). Non delayed data
mode is similar to long-frame timing on the
ETC5050/60 series of devices : time-slots being
nominally coincident with the rising edge of the ap-
propriate FS input. The alternative is to use De-
layed Data mode which is similar to short-frame
sync timing, in which each FS input must be high
at least a half-cycle of BCLK earlier than the time-
slot.
The Time-Slot Assignment circuit on the device can
only be used with Delayed Data timing. When using
Time-Slot Assignment, the beginning of the first
time-slot in a frame is identified by the appropriate
FS input. The actual transmit and receive time-slots
are then determined by the internal Time-Slot As-
signment counters. Transmit and Receive frames
and time-slots may be skewed from each other by
any number of BCLK cycles.
During each assigned transmit time-slot, the se-
lected DX0/1 output shifts data out from the PCM
register on the rising edges of BCLK. TSX0 (or
TSX1 as appropriate) also pulls low for the first 7
1/2 bit times of the time-slot to control the TRI-
STATE Enable of a backplane line driver. Serial
PCM data is shifted into the selected DR0/1 input
during each assigned Receive time slot on the
falling edges of BCLK. DX0 or DX1 and DR0 or
DR1 are selectable on the TS5070 only.
SERIAL CONTROL PORT
Control information and data are written into or
readback from COMBO IIG via the serial control
port consistingof the controlclock CCLK ; the serial
data input/ou tput CI/O (or separate input CI, and
output CO on the TS5070 only) ; and the Chip Se-
lect input CS. All control instructions require 2
bytes,as listed in table 1, with the exceptionof a sin-
gle byte power-up/down command. The byte 1 bits
are used as follows: bit 7 specifies power-up or
power-down; bits 6, 5, 4 and 3 specify the register
address; bit 2 specifies whether the instructions is
read or write; bit 1 specifies a one or two byte in-
7/32

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