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TTRN012G5 데이터시트 PDF




Agere Systems에서 제조한 전자 부품 TTRN012G5은 전자 산업 및 응용 분야에서
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부품번호 TTRN012G5 기능
기능 TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer/ 16:1 Data Multiplexer
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TTRN012G5 데이터시트, 핀배열, 회로
Preliminary Data Sheet
August 2000
TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s)
Clock Synthesizer, 16:1 Data Multiplexer
Features
s TTRN012G5 supports OC-48/STM-16 data rate
s TTRN012G7 supports:
— OC-48/STM-16 data rate
— RS (255, 239) forward error correction (FEC)
OC-48/STM-16 data rate
s Fully integrated clock synthesizer and 16:1 data
multiplexer
s Supports clockless data transfer into the 16:1
multiplexer
s Parity checking and valid data indication
s Data inversion option
s Additional high-speed CML serial data output for
system loopback
s Loss of lock indication
s Single 3.3 V supply
s Available in either MBIC 025 BiCMOS technology
or lower-power MBIC 025 silicon germanium
BiCMOS technology
s LVPECL 155.52 Mbits/s digital I/O
s Jitter generation and jitter transfer compliant with
the following:
Telcordia Technologies* GR-253
— ITU-T G.825
— ITU-T G.958
Applications
s SONET/SDH line origination equipment
s SONET/SDH add/drop multiplexers
s SONET/SDH cross connects
s SONET/SDH test equipment
s Digital video transmission
* Telcordia Technologies is a registered trademark of Bell Com-
munications Research, Inc.
Description
The Lucent Technologies Microelectronics Group
TTRN012G5 operates at the OC-48/STM-16 data
rate of 2.5 Gbits/s. The TTRN012G7 device operates
at either 2.5 Gbits/s or the RS FEC OC-48/STM-16
data rate of 2.7 Gbits/s. For clarity, this data sheet
refers to the TTRN012G5 serial data rate as
2.5 Gbits/s and the parallel data and reference clock
frequency as 155 MHz. (The precise rates are
2.48832 Gbits/s and 155.52 MHz.) When using the
TTRN012G7 at the FEC rate, the 2.5 Gbits/s data
rate should be interpreted as 2.7 Gbits/s and the par-
allel and clock frequency should be interpreted as
166 MHz. (The precise rates are 2.66606 Gbits/s and
166.62 MHz.)
The devices provide a 16:1 multiplexer and clock
multiplier unit. Both a high-speed serial clock and
data output are generated. The devices accept 16
differential PECL data inputs and a low-speed refer-
ence clock. A unique feature of the multiplexer is that
no clock is required to feed in the 16 data lines, as
long as the upstream data chip clock is synchronous
with the device REFCLKP/N input.
Alternatively, contra-clocking may be used, whereby
the device provides one of four phases of a
155.52 MHz or 166.62 MHz clock output back
upstream to the data chip.
Other features include a parity bit input and parity
check on the 16 input data lines, a second
2.5 Gbits/s or 2.7 Gbits/s data output for loopback
toward the TRCV012G5 or TRCV012G7 device, and
a user-configurable PLL bandwidth. Both devices are
available in either BiCMOS or in SiGe BiCMOS tech-
nology for lower power operation.




TTRN012G5 pdf, 반도체, 판매, 대치품
TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
Pin Information
Preliminary Data Sheet
August 2000
GND
VCCD
VCCD
GND
VCCD
TSTCKP
VCCD
TSTCKN
VCCD
TESTN
INVDATN
VCCD
GND
D2G5P
D2G5N
GND
CK2G5P
CK2G5N
GND
VCCD
ENCK2G5
RREF2
RREF1
VCCD
GND
LBDN
LBDP
GND
VCCD
ENLBDN
GND
GND
LCKLOSSN
VCCD
VCCD
NC
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102 GND
101 GND
100 GND
99 D15P
98 D15N
97 D14P
96 D14N
95 GND
94 D13P
93 D13N
92 D12P
91 D12N
90 VCCD
89 D11P
88 D11N
87 D10P
86 D10N
85 GND
84 D9P
83 D9N
82 D8P
81 D8N
80 VCCD
79 D7P
78 D7N
77 D6P
76 D6N
75 GND
74 D5P
73 D5N
72 D4P
71 D4N
70 VCCD
69 D3P
68 D3N
67 D2P
66 D2N
65 GND
Figure 2. Pin Diagram of 128-Pin QFP (Top View)
5-8066(F)r.3
4 Lucent Technologies Inc.

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TTRN012G5 전자부품, 판매, 대치품
Preliminary Data Sheet
August 2000
TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
Pin Information (continued)
Table 2. Pin Descriptions—155.52 Mbits/s and Related Signals (continued)
Pin Symbol* TypeLevel
Name/Description
53
CK155P
O LVPECL Clock Output (155 MHz). 155 MHz differential clock output.
52 CK155N
43
PHADJ1
Iu CMOS Phase Adjust. Adjusts phase of CK155P/N in 90 degree steps.
44 PHADJ0
42 CLKMODE Iu CMOS Clock Mode Select. Selects clockless data transfer mode.
0 = clockless transfer
1 or no connection = contra clock
57
PARITYP
I LVPECL Parity Input over Data (D[15:0]).
56 PARITYN
50
VALIDP
O LVPECL Parity Check Output. Validates the input of PARITYP/N.
49 VALIDN
0 = parity check does not agree with input PARITYP/N pins
1 = parity check agrees
33 LCKLOSSN O CMOS Loss of Lock (Active-Low). 0 = PLL out of lock.
41
EXTADJN
Iu CMOS External Automatic Phase Adjust (Active-Low). Adjusts the
155 MHz clock output, CK155P/N.
0 = adjust phase of 155 MHz clock to data upon next transition
of the D0P/N input signal
1 = no adjust
Must be held low until the first rising transition of D0P/N.
47 MONAPAP O LVPECL Monitor Automatic Phase Adjust. Indicates when a phase
46 MONAPAN
adjustment in the automatic phase adjust block occurs.
105 REFCLKP I LVPECL Reference Clock Input (155 MHz). This clock is required.
106 REFCLKN
When applying the REFCLKP/N, set the REFCLKP/N to one of
the following frequencies:
s 155.52 MHz if using the TRCV012G5, or the TRCV012G7 at
the 0C-48/STM-16 rate of 2.48832 GHz.
s 166.62 MHz if using the TRCV012G7 at the RS FEC
0C-48/STM-16 rate of 2.66606 GHz.
112 LFP I Analog Loop Filter PLL. Connect LFP to VCP, and LFN to VCN.
111 LFN
113 VCP I Analog VCO Control. Connect VCP to LFP, and VCN to LFN.
110 VCN
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. Iu indicates an internal pull-up resistor on this pin.
Lucent Technologies Inc.
7

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