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PDF TTRN012G73XE1 Data sheet ( Hoja de datos )
| Número de pieza | TTRN012G73XE1 | |
| Descripción | TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s) Clock Synthesizer/ 16:1 Data Multiplexer | |
| Fabricantes | Agere Systems | |
| Logotipo |  |
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Preliminary Data Sheet
August 2000
TTRN012G5 (2.5 Gbits/s) and TTRN012G7 (2.5 Gbits/s and 2.7 Gbits/s)
Clock Synthesizer, 16:1 Data Multiplexer
Features
s TTRN012G5 supports OC-48/STM-16 data rate
s TTRN012G7 supports:
— OC-48/STM-16 data rate
— RS (255, 239) forward error correction (FEC)
OC-48/STM-16 data rate
s Fully integrated clock synthesizer and 16:1 data
multiplexer
s Supports clockless data transfer into the 16:1
multiplexer
s Parity checking and valid data indication
s Data inversion option
s Additional high-speed CML serial data output for
system loopback
s Loss of lock indication
s Single 3.3 V supply
s Available in either MBIC 025 BiCMOS technology
or lower-power MBIC 025 silicon germanium
BiCMOS technology
s LVPECL 155.52 Mbits/s digital I/O
s Jitter generation and jitter transfer compliant with
the following:
— Telcordia Technologies* GR-253
— ITU-T G.825
— ITU-T G.958
Applications
s SONET/SDH line origination equipment
s SONET/SDH add/drop multiplexers
s SONET/SDH cross connects
s SONET/SDH test equipment
s Digital video transmission
* Telcordia Technologies is a registered trademark of Bell Com-
munications Research, Inc.
Description
The Lucent Technologies Microelectronics Group
TTRN012G5 operates at the OC-48/STM-16 data
rate of 2.5 Gbits/s. The TTRN012G7 device operates
at either 2.5 Gbits/s or the RS FEC OC-48/STM-16
data rate of 2.7 Gbits/s. For clarity, this data sheet
refers to the TTRN012G5 serial data rate as
2.5 Gbits/s and the parallel data and reference clock
frequency as 155 MHz. (The precise rates are
2.48832 Gbits/s and 155.52 MHz.) When using the
TTRN012G7 at the FEC rate, the 2.5 Gbits/s data
rate should be interpreted as 2.7 Gbits/s and the par-
allel and clock frequency should be interpreted as
166 MHz. (The precise rates are 2.66606 Gbits/s and
166.62 MHz.)
The devices provide a 16:1 multiplexer and clock
multiplier unit. Both a high-speed serial clock and
data output are generated. The devices accept 16
differential PECL data inputs and a low-speed refer-
ence clock. A unique feature of the multiplexer is that
no clock is required to feed in the 16 data lines, as
long as the upstream data chip clock is synchronous
with the device REFCLKP/N input.
Alternatively, contra-clocking may be used, whereby
the device provides one of four phases of a
155.52 MHz or 166.62 MHz clock output back
upstream to the data chip.
Other features include a parity bit input and parity
check on the 16 input data lines, a second
2.5 Gbits/s or 2.7 Gbits/s data output for loopback
toward the TRCV012G5 or TRCV012G7 device, and
a user-configurable PLL bandwidth. Both devices are
available in either BiCMOS or in SiGe BiCMOS tech-
nology for lower power operation.
1 page  
Preliminary Data Sheet
August 2000
TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
Pin Information (continued)
Table 1. Pin Descriptions—2.5 Gbits/s and Related Signals
Note: In Table 1, when operating the TTRN012G7 device at the OC-48/STM-16 rate, 2.5 Gbits/s should be inter-
preted as 2.48832 Gbits/s. When operating the TTRN012G7 device at the RS FEC OC-48/STM-16 rate,
2.5 Gbits/s should be interpreted as 2.66606 Gbits/s. (A similar interpretation should be made for 2.5 GHz.)
Pin Symbol* Type† Level
Name/Description
14
D2G5P
O CML Data Output (2.5 Gbits/s NRZ). 2.5 Gbits/s differential data
15 D2G5N
output.
27
LBDP
O CML Loopback Data Output. Additional 2.5 Gbits/s differential data
26 LBDN
output for system loopback.
17 CK2G5P O CML Clock Output (2.5 GHz). 2.5 GHz differential clock output.
18 CK2G5N
23
RREF1
I Analog Resistor Reference 1. CML current bias reference resistor.
(See Table 15, page 18 for values.)
22
RREF2
I Analog Resistor Reference 2. CML bias reference resistor. Connect a
1.5 kΩ resistor to VCCD.
21
ENCK2G5
Iu CMOS Enable CK2G5P/N Clock Output.
0 = CK2G5P/N buffer powered off
1 or no connection = CK2G5P/N buffer enabled
30
ENLBDN
Iu CMOS Enable LBDP/N Data Output (Active-Low).
0 = LBDP/N buffer enabled
1 or no connection = LBDP/N buffer powered off
11
INVDATN
Iu CMOS Invert D2G5P/N Data Output (Active-Low).
0 = invert
1 or no connection = noninvert
* Differential pairs are indicated by P and N suffixes. For nondifferential pins, N at the end of the symbol name designates active-low.
† I = input, O = output. Iu indicates an internal pull-up resistor on this pin.
Lucent Technologies Inc.
5
5 Page 
Preliminary Data Sheet
August 2000
TTRN012G5 and TTRN012G7
Clock Synthesizer, 16:1 Data Multiplexer
Functional Overview (continued)
Multiplexer Operation
The parallel 155 Mbits/s data is clocked into an input buffer by a 155 MHz clock derived from the synthesized
2.5 GHz clock. The data is checked for parity and then clocked into a 16:1 multiplexer. The relationship between
the parallel D[15:0] input data and the serial output data (D2G5P/N) is given in Figure 5. The D15 bit is the most
significant bit (MSB) and is shifted out first in time in the serial output stream.
D15
(MSB)
D14
(D15 SERIALLY SHIFTED OUT FIRST)
TIME
D1
D0
(LSB)
D15
(D0 SERIALLY SHIFTED OUT LAST)
Figure 5. Parallel Input to Serial Output Data Relationship
5-8063(F)
High-Speed Serial Clock Output Enable (ENCK2G5)
A separate output enable is provided for the 2.5 GHz clock output (CK2G5P/N). The enable is an active-high
CMOS input with an internal pull-up resistor. The default condition will enable the CK2G5P/N output, and applying
a ground or setting the enable pin (ENCK2G5) to logic low will disable the CK2G5P/N output. When disabled, the
CK2G5P/N output pins should be either left floating, or be connected to a load which returns to VCC. The output
must not be connected directly to ground when it is disabled.
Loopback 2.5 GHz Data Output (LBDP/N, ENLBDN)
An alternate 2.5 Gbits/s CML data output is available on the LBDP/N pin. This pin is provided for use in system
loopback testing and avoids the need for off-chip signal splitting of the data signal path. The alternate
2.5 Gbits/s loopback data output may be enabled by setting the ENLBDN pin to logic low. ENLBDN enable is an
active-low CMOS input with an internal pull-up resistor so the default condition will disable the LBDP/N output, and
a ground or logic-low signal must be applied to enable the loopback output. When disabled, the LBDP/N pin should
be either left floating, or be connected to a load which returns to VCC. The output must not be connected directly to
ground when it is disabled.
Parity Validation (VALIDP/N)
The parity signal is expected to be a logic 0 when the number of 1s in the 16-bit input register is an even number,
and the parity signal is expected to be a logic 1 when the number of 1s in the input register is an odd number. If the
parity bit agrees with the parity in the input register, then the VALIDP/N signal will be logic high. If the parity signal
is not generated, the VALIDP/N pin should be left open without termination to avoid meaningless signal swings and
avoid unnecessary power dissipation.
Lucent Technologies Inc.
11
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