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PDF TTSI1K16T Data sheet ( Hoja de datos )
| Número de pieza | TTSI1K16T | |
| Descripción | 1024-Channel/ 16-Highway Time-Slot Interchanger | |
| Fabricantes | Agere Systems | |
| Logotipo |  |
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Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Features
s Sixteen full-duplex, serial time-division multiplexed
(TDM) highways.
s Full availability, nonblocking 1024-channel time/
space switch.
s 2.048 Mbits/s (32 time slots), 4.096 Mbits/s (64
time slots), or 8.192 Mbits/s (128 time slots) data
rates, independently programmable per highway.
s 64 kbits/s granularity with optional 32 kbits/s (4-bit)
and 16 kbits/s (2-bit) subrate switching, selectable
per highway.
s Low-latency mode for voice channels.
s Frame integrity for wideband data applications.
s Concentration highway interface (CHI) compatible
with the IOM2, GCI, K2, SLD, MVIP*, ST-Bus,
SC-Bus, and H.100.
s Single highway clock and frame synchronization
input.
s Independently programmable bit and byte offsets
with 1/4 bit resolution for all highways.
s Capable of broadcasting data to the transmit high-
ways from a variety of sources including host data.
s High-impedance control per time slot.
s Software-compatible family of 1K, 2K, and 4K time-
slot interchangers.
s Sixteen independent high-impedance indicators
(output enables) for transmit highways, allowing
external drivers.
s Direct access to device registers, connection store,
and data store via microprocessor interface.
s IEEE†1149.1 boundary scan (JTAG).
s Test-pattern generation and checking for on-line
system testing (PRBS, QRSS, or user-defined
byte).
s User-accessible BIST for data and connection
stores.
s 3.3 V power supply with 5 V tolerant I/O.
s Low-power, high-density CMOS technology, and
TTL compatible switching thresholds.
s 144-pin TQFP package.
s –40 °C to +85 °C operating temperature range.
* MVIP is a registered trademark of Natural Microsystems Corpo-
ration.
† IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Applications
s Small and medium digital switch matrices.
s Computer telephony integration (CTI).
s Access concentrators.
s PABX.
s Cellular infrastructure.
s ISP modem banks.
s T1/E1 multiplexers.
s Digital cross connects.
s Digital loop carriers.
s Multiport DS1/E1 service cards.
s LAN/WAN gateways.
s TDM highway data rate adaptation.
Description
The TTSI1K16T Time-Slot Interchanger (TSI)
switches data between 16 full-duplex, serial, time-
division multiplexed highways. The TTSI1K16T can
make any connection between 1024 input and output
time slots.
Each of the 16 transmit and 16 receive highways can
be independently programmed for data rate
(2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s) and
offset. The offset can range from 0 bits to 127 bytes
and 7 3/4 bits on a 8.192 Mbits/s highway. The
TTSI1K16T can perform rate adaptation between
varying speed highways as well.
The TTSI1K16T is configured via a microprocessor
interface with a demultiplexed address and data bus.
In addition to accessing the registers and connection
store, this interface can also be used to read
received time slots and specify user data for trans-
mission.
The TTSI1K16T ensures that interchanged time slots
retain their frame integrity. Frame integrity is required
for applications that switch wideband data (i.e., ISDN
H-channels). For voice applications where low delay
is important, a low-latency mode can be selected.
1 page  
Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Functional Description
The TTSI1K16T is a 1024 time-slot switch that can be used in a variety of ways, with some or all of the highways
active and running at different data rates. The table below lists a few of the possible combinations of switch size
and data rates. By selecting different rates for receive and transmit highways, rate adaptation can be performed
also. Each one of the 32 (16 transmit and 16 receive) highways can be independently programmed for data rate
(2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s) as well as a full range of bit (0—7.75) and byte (0—127) offsets.
Table 1. Data Rate and Switch Size Examples
Number of
Receive
Highways
Used
16
8
8
8
and 4
Receive
Receive
Highway Data Time Slots
Rates (Mbits/s) per Frame
4.096
8.192
8.192
4.096
8.192
64
128
128
64
128
Total
Switch
Size
1024
1024
1024
1024
Number of
Transmit
Highways
Used
16
8
16
6
and 5
Transmit
Transmit
Highway Data Time Slots
Rates (Mbits/s) per Frame
4.096
8.192
4.096
4.096
8.192
64
128
64
64
128
This device uses a single clock (CK) and frame synchronization (FSYNC) signal for all highways. The CK rate can
be 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz, and this speed is indicated to the device via the CKSPD
[0—2] strap pins. A pulse is expected on the FSYNC pin once every 125 µs.
Each one of the 1024 time slots can be independently programmed in any one of the data modes listed below:
s Low latency
s Frame integrity
s Host data substitution
s Idle code substitution
s Test-pattern substitution (PRBS, QRSS, or a fixed byte)
s High impedance
The low-latency mode causes a receive highway time slot to be transmitted as soon as possible, which is depen-
dent on the relative offset of the input and output time slots. This mode is useful for voice channels where it is
important to keep the transmission delay to a minimum.
The frame integrity mode will guarantee that all selected time slots received in a common frame will be transmitted
together in a common frame. This mode is useful for wideband data (e.g., ISDN H-channels) where multiple time
slots received in a single frame cannot be split across two transmit frames.
The TTSI1K16T is a nonblocking DS0 (64 kbits/s channel) switch where a time slot is 8 bits. Since each Rx and Tx
highway data rate can be individually selected, the TTSI1K16T can also be used to switch time slots that are
smaller than 8 bits.
s 32 kbits/s channels (4-bit time slots) such as in compressed voice (ADPCM) applications. The TTSI1K16T will
be configured to sample the data at twice the data rate for highways carrying traffic at 2.048 Mbits/s or
4.096 Mbits/s.
s 16 kbits/s channels (2-bit time slots) such as in cellular (GSM) applications. The TTSI1K16T will be set to sample
the data at four times the data rate on a 2.048 Mbits/s highway carrying such traffic.
s 8 kbits/s channels (1-bit time slots) such as in half-rate GSM applications. This can be done by looping the data
through the TSI multiple times, thus oversampling the same data multiple times. However, in this configuration,
the total switching capacity of the device will drop and the latency will go up.
The TTSI1K16T is one in a family of 1K, 2K, and 4K TSIs. The high-impedance control per time-slot feature allows
four of the 4K devices to be connected to make an 8K time-slot switch.
If external drivers are needed on the transmit highway pins, support for 16 output enables, corresponding to the 16
transmit highways, is provided.
Lucent Technologies Inc.
5
5 Page 
Preliminary Data Sheet
February 1999
TTSI1K16T
1024-Channel, 16-Highway Time-Slot Interchanger
Pin Information (continued)
Table 4. TTSI1K16T Pin Descriptions (continued)
Symbol
Type*
Description
D[7—0]
I/O Host Processor Data Bus. These pins Host Processor Data Bus. These pins
provide an 8-bit, bidirectional data bus. provide an 8-bit, bidirectional data bus.
Read data is valid for one PCLK cycle Write data must be valid for the duration
coincident with the assertion of DT. Write of DS. Read data is valid while DT is
data must be held throughout the
asserted.
access.
A[14—0]
I Host Processor Address Bus. A14—A0 must remain valid throughout the entire
processor access. A0 is the least significant address signal and is used to select
byte locations.
R/W I Read/Write. This signal indicates a read or write cycle. Read cycle is indicated with
a logic 1; a write cycle is indicated with a logic 0.
INT O Interrupt. This pin will be asserted to indicate that an interrupt condition has
occurred. This output will remain active until the interrupt status register has been
cleared (read). The polarity of this output is controlled through the INTP bit (bit 3) of
the general command register. The default value of this register is 0, which indi-
cates active-high. This output is tristated until INTOE (bit 4) of the general command
register is set to 1. The polarity of this output should be selected before the pin is
enabled.
RXD[0—15]
Iu Receive Data Highways 0—15. Serial TDM highways receiving data at rates of
2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s.
FSYNC
I Frame Synchronization. This signal indicates the beginning of a frame every
125 µs (8 kHz). FSYNC can be active-low or active-high, but its polarity is the same
for all highways. FSYNC can be sampled on a positive or negative CK edge. Time-
slot numbers and bit offsets are assigned relative to the detection of FSYNC. There
are no restrictions on the duty cycle of FSYNC as long as the setup and hold timing
requirements relative to CK are met.
CK I Clock. This input is the clock reference for all the transmit and receive highways. Its
frequency can be 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz. The fre-
quency selection for CK must be set equal to or greater than the fastest highway
data rate.
CKSPD[2—0]
I Clock Speed Select for CK Pin. These strap pins indicate the frequency of CK:
CKSPD2
0
0
0
0
1
CKSPD1
0
0
1
1
X
CKSPD0
0
1
0
1
X
CK (MHz)
2.048
4.096
8.192
16.384
Reserved
TXD[0—15]
O Transmit Data Highways 0—15. Serial TDM highway transmitting data at rates of
2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. During external driver mode, the
TXD[0—15] outputs will be continuously driven. The only exception to this is when
the TEST input is asserted. When not in external driver mode, this highway can be
tristated on a per-time-slot basis.
See Table 41, Transmit Highway 3-State Options, on page 49 for a detailed descrip-
tion of all methods for 3-stating the transmit highways.
*Iu indicates internal 100 kΩ pull-up resistor, and Id indicates 17.5 kΩ pull-down resistor.
Lucent Technologies Inc.
11
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