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PDF TTSI4K32T Data sheet ( Hoja de datos )
| Número de pieza | TTSI4K32T | |
| Descripción | 4096-Channel/ 32-Highway Time-Slot Interchanger | |
| Fabricantes | Agere Systems | |
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Data Sheet
June 2000
TTSI4K32T
4096-Channel, 32-Highway Time-Slot Interchanger
Features
s Thirty-two full-duplex, serial time-division multi-
plexed (TDM) highways.
s Full availability, nonblocking 4096-channel time/
space switch.
s 2.048 Mbits/s (32 time slots), 4.096 Mbits/s (64
time slots), or 8.192 Mbits/s (128 time slots) data
rates, independently programmable per highway.
s 64 kbits/s granularity with optional 32 kbits/s (4-bit)
and 16 kbits/s (2-bit) subrate switching, selectable
per highway.
s Low-latency mode for voice channels.
s Frame integrity for wideband data applications.
s Concentration highway interface (CHI) compatible
with the IOM2, GCI, K2, SLD, MVIP*, ST-Bus,
SC-Bus, and H.100.
s Single highway clock and frame synchronization
input.
s Independently programmable bit and byte offsets
with 1/4 bit resolution for all highways.
s Capable of broadcasting data to the transmit high-
ways from a variety of sources including host data.
s High-impedance control per time slot.
s Software-compatible family of 1K, 2K, and 4K time-
slot interchangers.
s Thirty-two independent high-impedance indicators
(output enables) for transmit highways, allowing
external drivers.
s Direct access to device registers, connection store,
and data store via microprocessor interface.
s IEEE†1149.1 boundary scan (JTAG).
s Test-pattern generation and checking for on-line
system testing (PRBS, QRSS, or user-defined
byte).
s User-accessible BIST for data and connection
stores.
s 3.3 V power supply with 5 V tolerant I/O.
s Low-power, high-density CMOS technology, and
TTL compatible switching thresholds.
s 217-pin PBGA package.
s –40 °C to +85 °C operating temperature range.
* MVIP is a registered trademark of Natural Microsystems Corpo-
ration.
† IEEE is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
Applications
s Small and medium digital switch matrices.
s Computer telephony integration (CTI).
s Access concentrators.
s PABX.
s Cellular infrastructure.
s ISP modem banks.
s T1/E1 multiplexers.
s Digital cross connects.
s Digital loop carriers.
s Multiport DS1/E1 service cards.
s LAN/WAN gateways.
s TDM highway data rate adaptation.
Description
The TTSI4K32T Time-Slot Interchanger (TSI)
switches data between 32 full-duplex, serial, time-
division multiplexed highways. The TTSI4K32T can
make any connection between 4096 input and output
time slots.
Each of the 32 transmit and 32 receive highways can
be independently programmed for data rate
(2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s) and
offset. The offset can range from 0 bits to 127 bytes
and 7 3/4 bits on a 8.192 Mbits/s highway. The
TTSI4K32T can perform rate adaptation between
varying speed highways as well.
The TTSI4K32T is configured via a microprocessor
interface with a demultiplexed address and data bus.
In addition to accessing the registers and connection
store, this interface can also be used to read
received time slots and specify user data for trans-
mission.
The TTSI4K32T ensures that interchanged time slots
retain their frame integrity. Frame integrity is required
for applications that switch wideband data (i.e., ISDN
H-channels). For voice applications where low delay
is important, a low-latency mode can be selected.
1 page  
Data Sheet
June 2000
TTSI4K32T
4096-Channel, 32-Highway Time-Slot Interchanger
Functional Description
The TTSI4K32T is a 4096 time-slot switch that can be used in a variety of ways, with some or all of the highways
active and running at different data rates. The table below lists a few of the possible combinations of switch size
and data rates. By selecting different rates for receive and transmit highways, rate adaptation can be performed
also. Each one of the 64 (32 transmit and 32 receive) highways can be independently programmed for data rate
(2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s) as well as a full range of bit (0—7.75) and byte (0—127) offsets.
Table 1. Data Rate and Switch Size Examples
Number of
Receive
Highways
Used
32
16
32
16
and 16
Receive
Receive
Highway Data Time Slots
Rates (Mbits/s) per Frame
8.192
8.192
2.048
4.096
8.192
128
128
32
64
128
Total
Switch
Size
4096
2048
1024
3072
Number of
Transmit
Highways
Used
32
32
8
12
and 18
Transmit
Transmit
Highway Data Time Slots
Rates (Mbits/s) per Frame
8.192
4.096
8.192
4.096
8.192
128
64
128
64
128
This device uses a single clock (CK) and frame synchronization (FSYNC) signal for all highways. The CK rate can
be 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz, and this speed is indicated to the device via the CKSPD
[0—2] strap pins. A pulse is expected on the FSYNC pin once every 125 µs.
Each one of the 4096 time slots can be independently programmed in any one of the data modes listed below:
s Low latency
s Frame integrity
s Host data substitution
s Idle code substitution
s Test-pattern substitution (PRBS, QRSS, or a fixed byte)
s High impedance
The low-latency mode causes a receive highway time slot to be transmitted as soon as possible, which is depen-
dent on the relative offset of the input and output time slots. This mode is useful for voice channels where it is
important to keep the transmission delay to a minimum.
The frame integrity mode will guarantee that all selected time slots received in a common frame will be transmitted
together in a common frame. This mode is useful for wideband data (e.g., ISDN H-channels) where multiple time
slots received in a single frame cannot be split across two transmit frames.
The TTSI4K32T is a nonblocking DS0 (64 kbits/s channel) switch where a time slot is 8 bits. Since each Rx and Tx
highway data rate can be individually selected, the TTSI4K32T can also be used to switch time slots that are
smaller than 8 bits.
s 32 kbits/s channels (4-bit time slots) such as in compressed voice (ADPCM) applications. The TTSI4K32T will
be configured to sample the data at twice the data rate for highways carrying traffic at 2.048 Mbits/s or
4.096 Mbits/s.
s 16 kbits/s channels (2-bit time slots) such as in cellular (GSM) applications. The TTSI4K32T will be set to sample
the data at four times the data rate on a 2.048 Mbits/s highway carrying such traffic.
s 8 kbits/s channels (1-bit time slots) such as in half-rate GSM applications. This can be done by looping the data
through the TSI multiple times, thus oversampling the same data multiple times. However, in this configuration,
the total switching capacity of the device will drop and the latency will go up.
The TTSI4K32T is one in a family of 1K, 2K, and 4K TSIs. The high-impedance control per time-slot feature allows
four of the 4K devices to be connected to make an 8K time-slot switch.
If external drivers are needed on the transmit highway pins, support for 32 output enables, corresponding to the 32
transmit highways, is provided.
Lucent Technologies Inc.
5
5 Page 
Data Sheet
June 2000
TTSI4K32T
4096-Channel, 32-Highway Time-Slot Interchanger
Pin Information (continued)
Table 3. Pin Assignments for a 217-Pin PBGA—Signal Name Order (continued)
Signal Name
TXOE23
TXOE24
TXOE25
TXOE26
TXOE27
TXOE28
TXOE29
TXOE30
TXOE31
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDPLL
VSS
VSS
Pin
D13
G16
M14
G15
U13
U12
P11
T7
R7
A7
B11
C1
D6
D8
D10
D12
E15
F2
H4
H14
H16
K4
K14
L2
L15
M4
P5
P8
P10
R12
R17
T10
U6
G2
H1
A9
B2
B16
Signal Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSPLL
Pin
C3
C15
D4
D9
D14
H8
H9
H10
J4
J8
J9
J10
J14
K8
K9
K10
P4
P9
P14
R3
R15
T2
T16
M15
M16
A17
B8
Lucent Technologies Inc.
11
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