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PDF TZA3014VH Data sheet ( Hoja de datos )
| Número de pieza | TZA3014VH | |
| Descripción | 2.5 Gbits/s postamplifier with level detector | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TZA3014
2.5 Gbits/s postamplifier with level
detector
Product specification
Supersedes data of 2000 Aug 09
File under Integrated Circuits, IC19
2001 Jun 25
1 page  
Philips Semiconductors
2.5 Gbits/s postamplifier with level detector
Product specification
TZA3014
SYMBOL PIN
PAD TYPE(1)
DESCRIPTION
RSSI
LOS
n.c.
INV
n.c.
MUTE
GNDA
GNDp
26 34 O RSSI output
27 35 O-DRN output of LOS detector; direct drive to either positive or negative supplied
logic via internal 5 kΩ resistor
28 36 TTL not connected
29 37 TTL input to invert the signal at pins OUT and OUTQ; supports positive or
negative logic
30 38 TTL not connected
31 39 TTL input to mute the output signal on pins OUT (‘0’) and OUTQ (‘1’); supports
positive or negative logic
32 40
S ground for input and LOS detector
pad −
S ground pad (exposed die pad)
Note
1. Pin type abbreviations: O = output, I = input, S = power supply, TTL = logic input and O-DRN = open-drain output.
handbook, full pagewidth
VCCA 1
IN 2
INQ 3
VCCA 4
n.c. 5
n.c. 6
n.c. 7
n.c. 8
exposed pad
TZA3014HT
GNDp
24 VCCB
23 OUT
22 OUTQ
21 VCCB
20 n.c.
19 n.c.
18 n.c.
17 n.c.
MGU123
Fig.2 Pin configuration HTQFP32 package.
2001 Jun 25
5
5 Page 
Philips Semiconductors
2.5 Gbits/s postamplifier with level detector
Product specification
TZA3014
RSSI and LOS detection
The TZA3014 monitors the level of the input AC signal.
This function can prevent the output circuit from reacting to
noise in case there is no valid input signal, and can ensure
that only data is transmitted when there is sufficient input
signal for low bit error rate system operation.
The RSSI uses seven limiting amplifiers in a ‘successive
detection’ topology to closely approximate a logarithmic
response over a total range of 70 dB. The AC signal is
full-wave rectified by a detector at each amplifier stage.
Each detector output has a current driver followed by a
low-pass filter providing the first stage in the recovery of
the average value of the demodulated input signal. The
total current from each detector output is converted to a
voltage by an internal load resistor and then buffered.
When the RSSI output is used, input pin LOSTH is not to
be connected to GND (standby mode). The RSSI output
follows the internal 3 dB hysteresis of the LOS
comparator. The LOS comparator detects when the input
signal level rises above a programmable fixed threshold.
Then pin LOS gets a LOW-level. The threshold level is
determined by the voltage on pin LOSTH and by the level
of the input AC signal (see Fig.8). A filter with a nominal
time constant of 1 µs prevents noise spikes from triggering
the level detector.
The LOS comparator has an internal 3 dB hysteresis and
drives an open-drain circuit with a 5 kΩ internal resistor
allowing it to directly interface positive or negative logic
circuits (see Fig.9).
Its response is independent of the input signal polarity due
to the circuit design and to the demodulating action of the
detector which transforms the alternating input voltage to
a rectified and filtered quasi DC output signal. The
logarithmic voltage slope of the TZA3014 is
ϕ = 1/12.5 dB/mV and mostly is independent of temperature
and supply voltage due to four feedback loops in the
reference circuit. The LOS detector output voltage is
derived from Vref.
The sensitivity of the LOS detector is affected by the RMS
value of the input signal which, in its turn, depends on the
frequency.
VLOSTH can be calculated using the following formula:
VLOSTH = VRSSI =
VCC
+
0.458
–
SRSSI
×
20
log
2---V-6---Ei-(--p----–-p--)-8--
(1)
handbook, halfpa1g0e3
Vi ( s e ) (p-p)
(mV)
102
10
1
LOS
LOW-level
(3)
MGU129
(1)
(2)
LOS
HIGH-level
10−1
10 20 30 40 50 60 70
VLOSTH (% of Vref)
VCC −0.16 VCC −0.48
VCC −0.8 VCC −1.12
VRSSI (V)
(1) PRBS pattern input signal with a frequency <1 GHz.
(2) Linearity error typically 0.5 dB.
(3) ϕ = 1/12.5 dB/mV.
Fig.8 Loss of signal assert level.
Example: a 200 mV (p-p) single-ended 1.2 GB/s PRBS
input signal will have a VRSSI voltage of VCC − 1.013 V.
If the offset voltage of the first stage increases above a
certain level, the high DC gain of the amplifier circuit will
cause successive stages to limit prematurely. This is
prevented by the LOS detector offset control loop which
extends the lower end of the amplifier’s dynamic range.
The offset is automatically and continuously compensated
by a feedback path from the last stage. An offset at the
output of the logarithmic converter is equivalent to a
change of amplitude at the input.
Using DC-coupling, with signal absence, and VIN not equal
to VINQ (mute), the LOS detector detects full signal. Only
very small signals with an average value equal to zero, can
result into a zero output.
where SRSSI in [mV/dB]; VLOSTH, VRSSI and Vi(p-p) in [V].
2001 Jun 25
11
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| PDF Descargar | [ Datasheet TZA3014VH.PDF ] | |
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