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PDF TZA3044T Data sheet ( Hoja de datos )
| Número de pieza | TZA3044T | |
| Descripción | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
TZA3044T; TZA3044U
1.25 Gbits/s Gigabit Ethernet
postamplifiers
Objective specification
File under Integrated Circuits, IC19
1998 Jul 07
1 page  
Philips Semiconductors
1.25 Gbits/s Gigabit Ethernet postamplifiers
Objective specification
TZA3044T; TZA3044U
Bonding pad locations
handbook, full pagewidth
AGND
n.c.
AGND
1.58(1) DIN
mm DINQ
AGND
TEST
VCCA
3 2 1 32 31 30 29 28
4 27
5
6
7x
8
0
0
9y
10 TZA3044U
26
25
24
23
22
21
11 20
12 13 14 15 16 17 18 19
VCCD
TEST
DGND
DOUT
DOUTQ
DGND
TEST
DGND
(1) Typical value.
Pad size: 90 × 90 µm.
1.58 mm(1)
MGR242
Fig.3 Bonding pad locations: TZA3044U.
FUNCTIONAL DESCRIPTION
The TZA3044 accepts up to 1.25 Gbits/s Gigabit Ethernet
data streams, with amplitudes from 2 mV (p-p) up to
1 V (p-p) single-ended. The input signal will be amplified
and limited to differential PECL output levels (see Fig.1).
The input buffer A1 presents an impedance of
approximately 4.5 kΩ to the data stream on the inputs DIN
and DINQ. The input can be used both single-ended and
differential, but differential operation is preferred for better
performance.
Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3044, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.
An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
The outcome of this test is available at the PECL
outputs ST and STQ. This flag can also be used to prevent
the PECL outputs DOUT and DOUTQ from reacting to
noise in the absence of a valid input signal, by connecting
the output STQ to the input JAM. This insures that data will
only be transmitted when the input signal-to-noise ratio is
sufficient for low bit error rate system operation.
PECL logic
The logic level symbol definitions for PECL are shown in
Fig.4.
Input biasing
The input pins DIN and DINQ are DC biased at
approximately 2.55 V by an internal reference generator
(see Fig.5). The TZA3044 can be DC coupled, but AC
coupling is preferred. In case of DC coupling, the driving
source must operate within the allowable input signal
range (2.0 V to VCCA + 0.5 V). Also a DC offset voltage of
1998 Jul 07
5
5 Page 
Philips Semiconductors
1.25 Gbits/s Gigabit Ethernet postamplifiers
Objective specification
TZA3044T; TZA3044U
CHARACTERISTICS
For typical values Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient
temperature range and supply voltage range; all voltages with respect to ground; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Supply
VCC
ICCD
ICCA
Ptot
Tj
Tamb
supply voltage
digital supply current
analog supply current
total power dissipation
junction temperature
ambient temperature
note 1
note 1
Inputs: DIN and DINQ
Vi(se)(p-p)
input signal voltage
single-ended (peak-to-peak)
Vi(dif)(p-p)
input signal voltage
differential (peak-to-peak)
VI
VIO(eq)
absolute input signal voltage
equivalent input signal offset
voltage
VIO(cor)
input offset voltage correction note 2
range
Ri
Ci
Vn(i)(rms)
input resistance
input capacitance
equivalent input RMS noise
voltage
single-ended
single-ended
note 3
3
−
−
−
−40
−40
0.002
0.004
2.1
−
−5
2.9
−
−
3.3
18
15
110
−
+25
−
−
2.55
−
−
4.5
−
115
5.5
27
22
270
+120
+85
V
mA
mA
mW
°C
°C
1.0 V
2.0 V
VCCA + 0.5 V
50 µV
+5 mV
7.6 kΩ
2.5 pF
145 µV
Input signal level-detect: RSET
Iref
Vref
Vth(p-p)
reference current
reference voltage
programmability
(single-ended, peak-to-peak)
note 4
referred to VCCA
Vi = 200 kHz square
wave
hys hysteresis
electrically measured
RF filter resistance
tF filter time constant
CF = 0
PECL outputs: DOUT and DOUTQ
VOL
VOH
tr
tf
tw(p-p)
f-3dB(l)
f-3dB(h)
LOW-level output voltage
HIGH-level output voltage
rise time
fall time
pulse width distortion
low frequency −3 dB point
high frequency −3 dB point
RL = 50 Ω to VCC − 2 V
RL = 50 Ω to VCC − 2 V
20% to 80%
80% to 20%
5
−1.55
2
2
14
0.5
−
−1.5
−
3
25
1.0
VCC − 1840 −
VCC − 1100 −
− 150
− 100
−−
− 0.85
1 000
1 300
60
−1.45
12
4
41
2.0
µA
V
mV
dB
kΩ
µs
VCC − 1620
VCC − 900
250
mV
mV
ps
200 ps
30 ps
1.5 kHz
1 600
MHz
1998 Jul 07
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet TZA3044T.PDF ] | |
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