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PDF TZA3044U Data sheet ( Hoja de datos )
| Número de pieza | TZA3044U | |
| Descripción | SDH/SONET STM4/OC12 and 1.25 Gbits/s Gigabit Ethernet postamplifiers | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TZA3044; TZA3044B
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet
postamplifiers
Product specification
Supersedes data of 1999 Mar 16
File under Integrated Circuits, IC19
1999 Nov 03
1 page  
Philips Semiconductors
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
Product specification
TZA3044; TZA3044B
FUNCTIONAL DESCRIPTION
The TZA3044 accepts up to 1.25 Gbits/s data streams,
with amplitudes from 2 mV (p-p) up to 1.5 V (p-p)
single-ended. The input signal will be amplified and limited
to differential PECL output levels (see Fig.1).
The input buffer A1 presents an impedance of
approximately 4.5 kΩ to the data stream on the inputs DIN
and DINQ. The input can be used both single-ended and
differential, but differential operation is preferred for better
performance.
Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3044, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.
An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
The outcome of this test is available at the PECL
outputs ST and STQ (TTL for the TZA3044B). This flag
can also be used to prevent the PECL outputs DOUT and
DOUTQ from reacting to noise in the absence of a valid
input signal, by connecting pin STQ to pin JAM. This
guarantees that data will only be transmitted when the
input signal-to-noise ratio is sufficient for low bit error rate
system operation.
PECL logic
The logic level symbol definitions for PECL are shown in
Fig.4.
Input biasing
The inputs, pins DIN and DINQ, are DC biased at
approximately 2.1 V by an internal reference generator
(see Fig.5). The TZA3044 can be DC coupled, but AC
coupling is preferred. In case of DC coupling, the driving
source must operate within the allowable input signal
range (1.3 V to VCCA). Also a DC offset voltage of more
than a few millivolts should be avoided, since the internal
DC offset compensation circuit has a limited correction
range.
If AC coupling is used to remove any DC compatibility
requirement, the coupling capacitors must be large
enough to pass the lowest input frequency of interest.
For example, 1 nF coupling capacitors react with the
internal 4.5 kΩ input bias resistors to yield a lower −3 dB
frequency of 35 kHz. This then sets a limit on the
maximum number of consecutive pulses that can be
sensed accurately at the system data rate. Capacitor
tolerance and resistor variation must be included for an
accurate calculation.
DC-offset compensation
A control loop connected between the inputs of buffer A3
and amplifier A1 (see Fig.1) will keep the input of buffer A3
at its toggle point in the absence of any input signal.
Because of the active offset compensation which is
integrated in the TZA3044, no external capacitor is
required. The loop time constant determines the lower
cut-off frequency of the amplifier chain, which is set at
approximately 850 Hz.
Input signal level detection
The TZA3044 allows for user-programmable input signal
level detection and can automatically disable the switching
of the PECL outputs if the input signal is below a set
threshold. This prevents the outputs from reacting to noise
in the absence of a valid input signal, and insures that data
will only be transmitted when the signal-to-noise ratio of
the input signal is sufficient for low bit-error-rate system
operation. Complementary PECL (TTL for the TZA3044B)
flags (pins ST and STQ) indicate whether the input signal
is above or below the programmed threshold level.
The input signal is amplified and rectified before being
compared to a programmable threshold reference. A filter
is included to prevent noise spikes from triggering the level
detector. This filter has a nominal 1 µs time constant and
additional filtering can be achieved by using an external
capacitor between VCCA and pin CF (the internal driving
impedance nominally is 25 kΩ). The resultant signal is
then compared to a threshold current through pin RSET.
This current can be set by connecting an external resistor
between VCCA and pin RSET, or by forcing a current into
pin RSET (see Fig.6).
1999 Nov 03
5
5 Page 
Philips Semiconductors
SDH/SONET STM4/OC12 and
1.25 Gbits/s Gigabit Ethernet postamplifiers
Product specification
TZA3044; TZA3044B
CHARACTERISTICS
For typical values Tamb = 25 °C and VCC = 3.3 V; minimum and maximum values are valid over the entire ambient
temperature range and supply voltage range; all voltages are measured with respect to ground; unless otherwise
specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
Supply
VCC
ICCD
ICCA
Ptot
Tj
Tamb
supply voltage
digital supply current
analog supply current
total power dissipation
junction temperature
ambient temperature
notes 1 and 2
note 2
notes 1 and 2
Input signal pins DIN and DINQ
Vi(se)(p-p) single-ended input signal
voltage (peak-to-peak)
note 3
Vi(dif)(p-p) differential input signal
voltage (peak-to-peak)
note 3
VI
VIO(eq)
absolute input signal voltage
equivalent input signal offset
voltage
VIO(cor)
input offset voltage correction note 4; positive
note 4; negative
Ri
Ci
Vn(i)(rms)
input resistance
input capacitance
equivalent input RMS noise
voltage
single-ended
single-ended; note 5
notes 5 and 6
3
−
−
−
−40
−40
0.002
0.004
1.3
−
−
−
2.9
−
−
3.3
18
15
110
−
+25
−
−
2.1
−
3
−3
4.5
−
100
5.5
31
24
300
+125
+85
1.5
3.0
VCCA
50
−
−
7.6
2.5
145
V
mA
mA
mW
°C
°C
V
V
V
µV
mV
mV
kΩ
pF
µV
Input signal level detect pin RSET
IRSET
VRSET
Vth(p-p)
reference current
reference voltage
threshold adjusting range
(single-ended, peak-to-peak)
hys hysteresis
RF filter resistance
tF filter time constant
PECL output pins DOUT and DOUTQ
VOL
VOH
tr
tf
tPWD
f−3dB(l)
f−3dB(h)
LOW-level output voltage
HIGH-level output voltage
rise time
fall time
pulse width distortion
low frequency −3 dB point
high frequency −3 dB point
notes 5 and 7
referred to VCCA
Vi = 1.25 Gbits/s PRBS
27 − 1 sequence; note 5
electrically measured
CF = 0; note 5
note 8
note 8
20% to 80%; note 5
80% to 20%; note 5
note 5
note 9
5
VCCA − 1.65
2
2
14
0.5
VCC − 1.84
VCC − 1.1
−
−
−
−
−
−
VCCA − 1.5
−
3
25
1.0
−
−
200
200
−
0.85
1 000
60
VCCA − 1.4
12
6
41
2.0
VCC − 1.6
VCC − 0.9
250
250
30
1.5
−
µA
V
mV
dB
kΩ
µs
V
V
ps
ps
ps
kHz
MHz
1999 Nov 03
11
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet TZA3044U.PDF ] | |
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