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부품번호 | U3410 기능 |
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기능 | HEXFET Power MOSFET | ||
제조업체 | International Rectifier | ||
로고 | |||
전체 10 페이지수
l Logic Level Gate Drive
l Ultra Low On-Resistance
l Surface Mount (IRLR3410)
l Straight Lead (IRLU3410)
l Advanced Process Technology
l Fast Switching
l Fully Avalanche Rated
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve the
lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power
MOSFETs are well known for, provides the designer
with an extremely efficient device for use in a wide
variety of applications.
The D-PAK is designed for surface mounting using
vapor phase, infrared, or wave soldering techniques.
The straight lead version (IRFU series) is for through-
hole mounting applications. Power dissipation levels
up to 1.5 watts are possible in typical surface mount
applications.
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Thermal Resistance
RθJC
RθJA
RθJA
www.irf.com
Parameter
Junction-to-Case
Junction-to-Ambient (PCB mount) **
Junction-to-Ambient
G
PD - 91607B
IRLR/U3410
HEXFET® Power MOSFET
D
VDSS = 100V
RDS(on) = 0.105Ω
ID = 17A
S
D -P A K
T O -2 52 A A
I-P A K
TO -251AA
Max.
17
12
60
79
0.53
± 16
150
9.0
7.9
5.0
-55 to + 175
300 (1.6mm from case )
Typ.
–––
–––
–––
Max.
1.9
50
110
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
°C
Units
°C/W
1
5/11/98
IRLR/U3410
1400
1200
1000
C is s
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds S HO RTE D
C rss = C gd
C oss = C ds + C gd
800
600
Coss
400
Crss
200
0A
1 10 100
V DS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
15
ID = 9.0A
12
VDS = 80V
VDS = 50V
VDS = 20V
9
6
3
FOR TEST CIRCUIT
SEE FIGURE 13
0A
0 10 20 30 40 50
Q G , Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
TJ = 175°C
10
TJ = 25°C
1 VGS = 0V A
0.4 0.6 0.8 1.0 1.2 1.4
VSD , Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1000
OPERATION IN THIS AREA LIMITED
BY R DS(on)
100
10µs
10 100µs
TC = 25°C
TJ = 175°C
S ingle P ulse
1
1ms
10ms
1 10 100
VDS , Drain-to-Source Voltage (V)
A
1000
Fig 8. Maximum Safe Operating Area
www.irf.com
4페이지 IRLR/U3410
D.U.T
+
-
RG
Peak Diode Recovery dv/dt Test Circuit
+ Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
-
-
+
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
+
- VDD
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
VGS=10V *
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
Inductor Curent
Forward Drop
VDD
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
www.irf.com
7
7페이지 | |||
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부품번호 | 상세설명 및 기능 | 제조사 |
U3410 | HEXFET Power MOSFET | International Rectifier |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |