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U4223B-MFS PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 U4223B-MFS
기능 Time-Code Receiver with A/D Converter
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U4223B-MFS 데이터시트, 핀배열, 회로
Time-Code Receiver with A/D Converter
U4223B
Description
The U4223B is a bipolar integrated straight-through receiver circuit in the frequency range of 40 kHz to 80 kHz.
The device is designed for radio-controlled clock applications.
Features
D Very low power consumption
D Very high sensitivity
D High selectivity by using two crystal filters
D Power-down mode available
D Only a few external components necessary
D 4-bit digital output
D AGC hold mode
Block Diagram
PON CLK D3 D2 D1 D0
VCC 1
GND
3
IN 2
16
Power supply
12 17 18 19
ADC
AGC
amplifier
Impulse
circuit
4 5 6 14 15
SB Q1A Q1B Q2A Q2B
20 11 FLB
Decoder
10 FLA
9 DEC
Rectifier & 13
integrator
78
REC INT
SL
Figure 1. Block diagram
Ordering and Package Information
Extended Type Number
U4223B-MFS
U4223B-MFSG3
T4223B-MF
T4223B-MC
Package
SSO20 plastic
SSO20 plastic
No
No
Remarks
Taping according to IEC-286-3
Die on foil
Die on carrier
Rev. A7, 06-Mar-01
1 (18)




U4223B-MFS pdf, 반도체, 판매, 대치품
U4223B
Q2A, Q2B
According to Q1A/Q1B, a crystal is connected between
the Pins Q2A and Q2B. It is used with the serial resonant
frequency of the time-code transmitter (e.g., 60 kHz
WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equiva-
lent parallel capacitor of the filter crystal is internally
compensated. The value of the compensation is about
0.7 pF.
Q2A Q2B
Figure 11.
GND
PON
If PON is connected to GND, the receiver will be
activated. The set-up time is typically 0.5 s after applying
GND at this pin. If PON is connected to VCC, the receiver
will switch to power-down mode.
A sequence of the digitalized time-code signal can be
analyzed by a special noise-suppressing algorithm in
order to increase the sensitivity and the signal-to-noise
ratio (more than 10 dB compared to conventional
decoding). Details about the time-code format are
described separately.
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Gray
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
VCC
VCC
PON
D0 ... D3
PON
Figure 12.
Figure 13.
GND
D0, D1, D2, D3
The outputs of the ADC consist of PNP-NPN push-pull
stages and can be directly connected to a microcomputer.
In order to avoid any interference of the output into the
antenna circuit, we recommend terminating each digital
output with a capacitor of 10 nF. The digitalized signal of
the ADC is Gray coded (see table). It should be taken into
account that in power-down mode (PON = high), D0, D1,
D2 and D3 will be high.
CLK
The input of the ADC is switched to the AGC voltage by
the rising slope of the clock. When conversion time has
passed (about 1.8 ms at 25°C), the digitalized field-
strength signal is stored in the output registers D0 to D3
as long as the clock is high and can be read by a micro-
computer. The falling slope of the clock switches the
input of the ADC to the time-code signal. In the mean-
time, the digitalized time-code signal is stored in the
output registers D0 to D3 as long as the clock is low (see
figure 14).
4 (18)
Rev. A7, 06-Mar-01

4페이지










U4223B-MFS 전자부품, 판매, 대치품
U4223B
Parameters
Test Conditions / Pin
Symbol Min Typ Max Unit
ADC; D0, D1, D2, D3 Pins 17, 18, 19 and 20
Output voltage HIGH
LOW
Output current HIGH
LOW
Input current into DEC
(first bit)
RLOAD = 870 kW to GND
RLOAD = 650 kW to VCC
VTCO = VCC/2
VTCO = VCC/2
Falling slope of CLK
VOH
VOL
VCC-0.4
V
0.4 V
ISOURCE
ISINK
3
4
10
12
mA
mA
Idecs –24 –17 –11 nA
Input current into DEC
(last bit)
Falling slope of CLK
Idece 28 35 42 nA
Input current into DEC
(step range)
Falling slope of CLK
Idecst 1.75 3.5 7 nA
Input voltage at IN
(first bit)
Input voltage at IN
(last bit)
Input voltage at IN
(step range)
Clock input; CLK
RF generator at IN, without
modulation rising slope of CLK
RF generator at IN, without
modulation rising slope of CLK
RF generator at IN, without
modulation rising slope of CLK
Pin 12
Vmin
Vmax
Vstep
–10 dBmV
75 dBmV
5.5 dBmV
Input voltage swing
Clock frequency
Dynamical input resistance
Power-ON/OFF control; PON
Pin 16
Vswing 50 100 VCC mV
fclk 100 125 Hz
Rdyn. 100 kW
Input voltage
Input current
HIGH
LOW
Set-up time after PON
Required IIN y 0.5 mA
VCC = 3 V
VCC = 1.5 V
VCC = 5 V
VCC-0.2
V
VCC-1.2 V
IIN 1.4 1.7 2 mA
0.7 mA
3 mA
t
0.5 2
s
AGC hold mode; SL Pin 13
Input voltage
Input current
HIGH
LOW
Rejection of interference
signals
Required IIN y 0.5 mA
Vin = VCC
Vin = GND
ȧfd – fudȧ = 625 Hz
Vd = 3 mV, fd = 77.5 kHz
using 2 crystal filters
using 1 crystal filter
VCC-0.2
V
VCC-1.2 V
0.1 mA
2.5 mA
af 43 dB
af 22 dB
Rev. A7, 06-Mar-01
7 (18)

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