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U4224B-CFLG3 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 U4224B-CFLG3
기능 Time Code Receiver
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U4224B-CFLG3 데이터시트, 핀배열, 회로
Time Code Receiver
U4224B
Description
The U4224B is a bipolar integrated straight through receiver circuit in the frequency range of 40 to 80 kHz.
The device is designed for radio controlled clock applications.
Features
D Very low power consumption
D Very high sensitivity
D High selectivity by using two crystal filters
D Power down mode available
D Only a few external components necessary
D Digitalized serial output signal
D AGC hold mode
Block Diagram
GND 3
VCC 1
PON
15
Power Supply
TCO
16
93 7727 e
Decoder
11 FLB
10 FLA
9 DEC
IN 2
AGC
Amplifier
4 5 6 13
SB Q1A Q1B Q2A
14
Q2B
Rectifier & 12 SL
Integrator
7
REC
8
INT
TELEFUNKEN Semiconductors
Rev. A3, 02-Apr-96
1 (17)




U4224B-CFLG3 pdf, 반도체, 판매, 대치품
U4224B
Q2A, Q2B
According to Q1A, Q1B a crystal is connected between
the pins Q2A and Q2B. It is used with the serial resonance
frequency of the time code transmitter (e.g. 60 kHz
WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equi-
valent parallel capacitor of the filter crystal is internally
compensated. The value of the compensation is about
0.7 pF.
Q2A
94 8383
Q2B
GND
PON
If PON is connected to GND, the U 4224 B receiver IC
will be activated. The set-up time is typical 0.5s after
applying GND at this pin. If PON is connected to VCC, the
receiver will go into power down mode.
VCC
PON
94 8373
TCO
The digitized serial signal of the time code transmitter can
be directly decoded by a microcomputer. Details about
the time code format of several transmitters are described
separately.
*The output consists of a PNP NPN push-pull-stage. It
should be taken into account that in the power down mode
(PON = high) TCO will be high.
VCC
PON
TCO
94 8380
GND
An additional improvement of the driving capability may
be achieved by using a CMOS driver circuit or a NPN
transistor with pull-up resistor connected to the collector
(see figure KEIN MERKER). Using a CMOS driver this
circuit must be connected to VCC.
VCC
100 kW
10 kW
TCO
pin16
TCO
94 8395 e
Figure 1.
Please note:
The signals and voltages at the pins REC, INT, FLA, FLB,
Q1A, Q1B, Q2A and Q2B cannot be measured by stan-
dard measurement equipment due to very high internal
impedances. For the same reason the PCB should be pro-
tected against surface humidity.
Design Hints for the Ferrite Antenna
The bar antenna is a very critical device of the complete
clock receiver. But by observing some basic RF design
W Wknowledge, no problem should arise with this part. The IC
requires a resonance resistance of 50 k to 200 k . This
can be achieved by a variation of the L/C-relation in the
antenna circuit. But it is not easy to measure such high
resistances in the RF region. It is much more convenient
to distinguish the bandwidth of the antenna circuit and
afterwards to calculate the resonance resistance.
Thus the first step in designing the antenna circuit is to
measure the bandwidth. Figure 4 shows an example for
the test circuit. The RF signal is coupled into the bar
antenna by inductive means, e.g. a wire loop. It can be
measured by a simple oscilloscope using the 10:1 probe.
The input capacitance of the probe, typically about 10 pF,
should be taken into consideration. By varying the
frequency of the signal generator, the resonance
frequency can be determined.
RF - Signal
generator
77.5 kHz
wire loop
Cres
Scope
Probe
w10
10
M: 1W
94 7907 e
4 (17)
TELEFUNKEN Semiconductors
Rev. A3, 02-Apr-96

4페이지










U4224B-CFLG3 전자부품, 판매, 대치품
U4224B
Parameters
Decoding characteristics
Test Conditions / Pin
JG2AS based on the values of
the application circuit
page KEIN MERKER:
TCO pulse width 200 ms
TCO pulse width 500 ms
TCO pulse width 800 ms
Delay compared with the
transient of the RF signal:
start transition (RF on)
end transition (RF off)
POWER ON/OFF CONTROL; PON pin 15
yInput voltage
Required IIN 0.5 mA
HIGH
LOW
Input current
Set-up time after PON
VCC = 3V
VCC = 1.5 V
VCC = 5 V
AGC HOLD MODE; SL
Input voltage
HIGH
LOW
ypin 12
Required IIN 0.5 mA
Input current
Rejection of interference
signals
Vin = VCC
ȧ ȧVin = GND
fd – fud = 625 Hz
Vd = 3 mV, fd = 77.5 kHz
using 2 crystal filters
using 1 crystal filter
Symbol Min.
t200 240
t500 420
t800 720
ts 10
te 30
VCC - 0.2
IIN 1.4
t
VCC - 0.2
af
af
Typ. Max. Unit
410 ms
490 ms
790 ms
110 ms
220 ms
V
VCC - 1.2 V
1.7 2 mA
0.7 mA
3 mA
0.5 2
s
V
VCC - 1.2 V
0.1 mA
2.5 mA
43 dB
22 dB
TELEFUNKEN Semiconductors
Rev. A3, 02-Apr-96
7 (17)

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부품번호상세설명 및 기능제조사
U4224B-CFLG3

Time Code Receiver

TEMIC Semiconductors
TEMIC Semiconductors

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