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TSL202R 데이터시트 PDF




ETC에서 제조한 전자 부품 TSL202R은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 TSL202R 기능
기능 128 *1 LINEAR SENSOR ARRAY
제조업체 ETC
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TSL202R 데이터시트, 핀배열, 회로
t
t
D 128 × 1 Sensor-Element Organization
D 200 Dots-Per-Inch (DPI) Sensor Pitch
D High Linearity and Uniformity
D Wide Dynamic Range . . . 2000:1 (66 dB)
D Output Referenced to Ground
D Low Image Lag . . . 0.5% Typ
D Operation to 5 MHz
D Single 5-V Supply
D Replacement for TSL202
TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032B – AUGUST 2002
(TOP VIEW)
VDD 1
SI1 2
CLK 3
AO1 4
GND 5
SO2 6
NC 7
ÉÉÉÉÉÇÇÇÇÇÉÉÉÉÉÇÇÇÇÇ
14 NC
13 SO1
12 GND
11 NC
10 SI2
9 NC
8 AO2
NC – No internal connection
Description
The TSL202R linear sensor array consists of two sections of 64 photodiodes and associated charge amplifier
circuitry arranged to form a contiguous 128 × 1 array. The pixels measure 120 µm (H) by 70 µm (W) with 125-µm
center-to-center spacing and 55-µm spacing between pixels. Operation is simplified by internal control logic that
requires only a serial-input (SI) signal and a clock.
The TSL202R is intended for use in a wide variety of applications including mark detection and code reading,
optical character recognition (OCR) and contact imaging, edge detection and positioning as well as optical linear
and rotary encoding.
Functional Block Diagram (each section — pin numbers apply to section 1)
Pixel 1
Integrator
Reset
_
+
Sample/
Output
Pixel
2
Pixel
3
Pixel
64
Analog
Bus
Output
Amplifier
1
VDD
4
AO
5
GND
RL
(External
330 W
Load)
Switch Control Logic
Q1 Q2 Q3
Gain
Trim
Q64
3
CLK
SI 2
64-Bit Shift Register
The LUMENOLOGYr Company
t
Texas Advanced Optoelectronic Solutions Inc.
800 Jupiter Road, Suite 205 S Plano, TX 75074 S (972t) 673-0759
www.taosinc.com
Copyright E 2002, TAOS Inc.
1




TSL202R pdf, 반도체, 판매, 대치품
TSL202R
128 y 1 LINEAR SENSOR ARRAY
TAOS032B – AUGUST 2002
Electrical Characteristics at fclock = 1 MHz, VDD = 5 V, TA = 25°C, λp = 640 nm, tint = 5 ms,
RL = 330 , Ee = 16.5 µW/cm2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Vout
Vdrk
PRNU
Analog output voltage (white, average over 128 pixels)
Analog output voltage (dark, average over 128 pixels)
Pixel response nonuniformity
See Note 1
See Notes 2 & 3
1.6 2 2.4 V
0 50 150 mV
±4% ±10%
Nonlinearity of analog output voltage
See Note 3
±0.4%
FS
Output noise voltage
See Note 4
1 mVrms
Re Responsivity
V/
18 23 30 J/cm2)
SE Saturation exposure
See Note 5
142 nJ/cm2
Vsat Analog output saturation voltage
DSNU Dark signal nonuniformity
All pixels
2.5 3.4
V
See Note 6
25 120 mV
IL Image lag
See Note 7
0.5%
IDD Supply current, output idle
IIH High-level input current
IIL Low-level input current
VOH High-level output voltage, SO1 and SO2
VI = VDD
VI = 0
IO = 50 µA
IO = 4 mA
5
4.5 4.95
4.6
8 mA
10 µA
10 µA
V
VOL Low-level output voltage, SO1 and SO2
IO = 50 µA
IO = 4 mA
0.01 0.1
V
0.4
Ci(SI) Input capacitance, SI
5 pF
Ci(CLK) Input capacitance, CLK
10 pF
NOTES: 1. The array is uniformly illuminated with a diffused LED source having a peak wavelength of 640 nm.
2. PRNU is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of the
device under test when the array is uniformly illuminated at the white irradiance level. PRNU includes DSNU.
3. Nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent
of analog output voltage (white).
4. RMS noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period.
5. Minimum saturation exposure is calculated using the minimum Vsat, the maximum Vdrk, and the maximum Re.
6. DSNU is the difference between the maximum and minimum output voltage in the absence of illumination.
7. Image lag is a residual signal left in a pixel from a previous exposure. It is defined as a percent of white-level signal remaining after
a pixel is exposed to a white condition followed by a dark condition:
IL
+
Vout (IL) * Vdrk
Vout (white) * Vdrk
100
Timing Requirements (see Figure 1 and Figure 2)
tsu(SI) Setup time, serial input (see Note 8)
th(SI) Hold time, serial input (see Note 8 and Note 9)
tw Pulse duration, clock high or low
tr, tf Input transition (rise and fall) time
NOTES: 8. Input pulses have the following characteristics: tr = 6 ns, tf = 6 ns.
9. SI must go low before the rising edge of the next clock pulse.
MIN NOM MAX UNIT
20 ns
0 ns
50 ns
0 500 ns
Copyright E 2002, TAOS Inc.
4
t
www.taosinc.com
The LUMENOLOGYr Company
t

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TSL202R 전자부품, 판매, 대치품
TSL202R
128 y 1 LINEAR SENSOR ARRAY
APPLICATION INFORMATION
TAOS032B – AUGUST 2002
Power Supply Considerations
For optimum device performance, power-supply lines should be decoupled by a 0.01-µF to 0.1-µF capacitor
with short leads mounted close to the device package (see Figure 5 and Figure 6).
Connection Diagrams
VDD
0.1 µF
SI
CLK
TSL202R
1
2 VDD
3 SI1
4 CLK
5 AO1
6 GND
7 SO2
VDD
NC
SO1
GND
NC
SI2
NC
AO2
14
13
12
11
10
9
8
AO
RL
Figure 5. Serial Connection
Si
CLK
AO1 (Pixels 1–64)
0.1 µF
RL
VDD
TSL202R
1
2 VDD
3 SI1
4 CLK
5 AO1
6 GND
7 SO2
VDD
NC
SO1
GND
NC
SI2
NC
AO2
14
13
12
11
10
9
8
Figure 6. Parallel Connection
AO2 (Pixels 65–128)
RL
The LUMENOLOGYr Company
t
www.taosinc.com
t
Copyright E 2002, TAOS Inc.
7

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