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PDF TS3V555 Data sheet ( Hoja de datos )
| Número de pieza | TS3V555 | |
| Descripción | 3V LOW POWER SINGLE TIMERS | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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TS3V555
3V LOW POWER SINGLE TIMERS
. DEDICATED TO 3.3V OR BATTERY SUPPLY
(Specified at 3V and 5V)
. VERY LOW POWER CONSUMPTION :
90µA at VCC = 3V
. WIDE SINGLE SUPPLY RANGE :
+2.7V to +16V
. HIGH OUTPUT CURRENT CAPABILITY
. SUPPLY CURRENT SPIKES REDUCED
DURING OUTPUT TRANSITIONS
. HIGH INPUT IMPEDANCE : 1012 Ω
. PIN-TO-PIN AND FUNCTIONALLY COMPAT-
. IBLE WITH BIPOLAR NE555 AND CMOS
TS555
OUTPUT COMPATIBLE WITH TTL,CMOS
AND LOGIC MOS
DESCRIPTION
The TS3V555 with its low consumption (90µA at
VCC = 3V) is a single CMOS timer dedicated to 3.3V
or battery supply (specified at 3V and 5V) offering
also a high frequency (f(max) 2MHz at VCC = 3V and
2.7 MHz at VCC = 5V). Thus, either in monostable
or astable mode, timing remains very accurate.
Timing capacitors can also be minimized due to
high input impedance (1012 Ω).
N
DIP8
(Plastic Package)
D
SO8
(Plastic Micropackage)
ORDER CODES
Part Number
TS3V555I
Temperature
Range
-40, +125oC
Package
ND
qq
PIN CONNECTIONS (top view)
GND
Trigger
Output
Reset
1
2
3
4
8 VCC
7 Discharge
6 Threshold
5
Control
Voltage
October 1997
1/8
1 page  
TS3V555
TYPICAL CHARACTERISTICS
Figure 1 : Supply Current (each timer)
versus supply voltage.
300
200
100
0 4 8 12 16
SUPPLY VOLTAGE, VCC (V)
APPLICATION INFORMATION
MONOSTABLE OPERATION
In the monostable mode,the timer functions as a
one-shot. Referring to figure 2 the external capaci-
tor is initially held discharged by a transistor inside
the timer.
Figure 2
VCC
Reset
Trigger
4
2
8
7
R
TS3V555 6
C
The circuit triggers on a negative-goinginput signal
when the level reaches 1/3 VCC. Once triggered,the
circuit remains in this state until the set time has
elapsed,even if it is triggered again during this
interval. The duration of the output HIGH state is
given by t = 1.1 R x C.
Notice that since the charge rate and the threshold
level of the comparator are both directly propor-
tional to supply voltage, the timing interval is inde-
pendent of supply. Applying a negative pulse
simultaneouslyto the Reset terminal (pin 4) and the
Trigger terminal (pin 2) during the timing cycle
discharges the external capacitor and causes the
cycle to start over. The timing cycle now starts on
the positive edge of the reset pulse. During the time
the reset pulse is applied, the output is driven to its
LOW state.
When a negative trigger pulse is applied to pin 2,
the flip-flop is set, releasing the short circuit across
the external capacitor and driving the output HIGH.
The voltage across the capacitor increases expo-
nentially with the time constant τ = R x C.
When the voltage across the capacitor equals 2/3
VCC, the comparator resets the flip-flop which then
discharges the capacitor rapidly and drives the
output to its LOW state.
Figure 3 shows the actual waveforms generated in
this mode of operation.
When Reset is not used, it should be tied high to
avoid any possible or false triggering.
Figure 3
t = 0.1 ms / div
INPUT = 2.0V/div
Out 3
5
Control Voltage
1 0.01µF
OUTPUT VOLTAGE = 5.0V/div
CAPACITOR VOLTAGE = 2.0V/div
R = 9.1kΩ, C = 0.01µ F , RL = 1.0kΩ
5/8
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| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet TS3V555.PDF ] | |
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