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PDF TS3V556I Data sheet ( Hoja de datos )
| Número de pieza | TS3V556I | |
| Descripción | 3V LOW POWER DUAL TIMERS | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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® TS3V556
3V LOW POWER DUAL TIMERS
. DEDICATED TO 3.3V OR BATTERY SUPPLY
(Specified at 3V and 5V)
. VERY LOW POWER CONSUMPTION :
90 A/tim at VCC = 3V
. WIDE SINGLE SUPPLY RANGE :
+2.7V to +16V
. HIGH OUTPUT CURRENT CAPABILITY
. SUPPLY CURRENT SPIKES REDUCED
DURING OUTPUT TRANSITIONS
. HIGH INPUT IMPEDANCE : 1012
. PIN-TO-PIN AND FUNCTIONALLY COMPATI-
. BLE WITH BIPOLAR NE556 AND CMOS
TS556
OUTPUT COMPATIBLE WITH TTL,CMOS
AND LOGIC MOS
DESCRIPTION
The TS3V556 with its low consumption (90µA/tim
at VCC = 3V) is a dual CMOS timer dedicated to
3.3V or battery supply(specified at 3V and 5V offer-
ing also a high frequency (f(max) 2MHz at VCC = 3V
and 2.7 MHz at VCC = 5V). Thus, either in mono-
stable or astable mode, timing remains very accu-
rate.
Timing capacitors can also be minimized due to
high input impedance (1012 Ω).
N
DIP14
(Plastic Package)
D
SO14
ORDER CODES
Part Number
TS3V556I
Temperature
Range
-40, +125oC
Package
ND
ll
PIN CONNECTIONS (top view)
May 2000
Discharge 1
T hre s hold 2
Contro l Voltage 3
Reset 4
Ou tput 5
Tr ig ger 6
GND 7
1 4 VC C
1 3 Discharge
1 2 Threshold
1 1 Contro l Voltag e
1 0 Re se t
9 Output
8 Trigger
1/8
1 page  
TS3V556
TYPICAL CHARACTERISTICS
Figure 1 : Supply Current (each timer)
versus supply voltage.
300
200
100
0 4 8 12 16
SUPPLY VOLTAGE, VCC (V)
APPLICATION INFORMATION
MONOSTABLE OPERATION
In the monostable mode,the timer functions as a
one-shot. Referring to figure 2 the external capaci-
tor is initially held discharged by a transistor inside
the timer.
Figure 2
VC C
Reset
R
Trigger
Out
1/2
TS3V556
C
Control Voltage
0.01µF
The circuit triggers on a negative-going input signal
when the level reaches 1/3 VCC. Once triggered,the
circuit remains in this state until the set time has
elapsed,even if it is triggered again during this in-
terval. The duration of the output HIGH state is
given by t = 1.1 R x C.
Notice that since the charge rate and the threshold
level of the comparator are both directly propor-
tional to supply voltage, the timing interval is inde-
pendent of supply. Applying a negative pulse
simultaneously to the Reset terminal (pin 4 or 10)
and the Trigger terminal (pin 2 or 8) during the tim-
ing cycle discharges the external capacitor and
causes the cycle to start over. The timing cycle now
starts on the positive edge of the reset pulse. Dur-
ing the time the reset pulse is applied, the output is
driven to its LOW state.
When a negative trigger pulse is applied to the trig-
ger terminal, the flip-flop is set, releasing the short
circuit across the external capacitor and driving the
output HIGH. The voltage across the capacitor in-
creases exponentiallywith the time constant τ = R x
C.
When the voltage across the capacitor equals 2/3
VCC, the comparator resets the flip-flop which then
discharges the capacitor rapidly and drives the out-
put to its LOW state.
Figure 3 shows the actual waveforms generated in
this mode of operation.
When Reset is not used, it should be tied high to
avoid any possible or false triggering.
Figure 3
t = 0.1 ms / div
INPUT = 2.0V/div
OUTPUT VOLTAGE = 5.0V/div
CAPACITOR VOLTAGE = 2.0V/div
R = 9.1kΩ, C = 0.01µ F , RL = 1.0k Ω
5/8
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet TS3V556I.PDF ] | |
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