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PDF TS68302VR16 Data sheet ( Hoja de datos )
| Número de pieza | TS68302VR16 | |
| Descripción | Integrated Multiprotocol Processor IMP | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• TS68000/TS68008 Microprocessor Core Supporting a 16- or 8-bit TS68000 Family
• System Integration Block Including:
– Independent Direct Memory Access (IDMA) Controller
– Interrupt Controller with Two Modes of Operation
– Parallel Input/output (I/O) Ports, some with Interrupt Capability
– On-chip Usable 1152 bytes of Dual-port Random-access Memory (RAM)
– Three Timers, including a Watchdog Timer
– Four Programmable Chip-select Lines with Wait-state Logic
– Programmable Address Mapping of Dual-port RAM and IMP Registers
– On-chip Clock Generator with an Output Clock Signal
– System Control:
System Control Register
Bus Arbitration Logic with Low Interrupt Latency Support
Hardware Watchdog for Monitoring Bus Activity
Low Power (Standby) Modes
Disable CPU Logic (TS68000)
Freeze Control for Debugging Selected On-chip Peripherals
DRAM Refresh Controller
• Communications Processor Including:
– Main Controller (RISC Processor)
– Three Full-duplex Serial Communication Controllers (SCCs)
– Six Serial Direct Memory Access (SDMA) Channels Dedicated to the Three SCCs
– Flexible Physical Interface Accessible by SCCs for Interchip Digital Link (IDL)
General Circuit Interface (GCI, see note), Pulse Code Modulation (PCM), and
Nonmultiplexed Serial Interface (NMSI) Operation
– Serial Communication Port (SCP) for Synchronous Communication, Clock Rate up
to 4.096 MHz
– Serial Management Controllers (SMCs) for IDL and GCI Channels
• Frequency of Operation: 16.67 MHz
• Power Supply: 5 VDC ± 10%
Description
The IMP is a very large-scale integration (VLSI) device incorporating the main building
blocks needed for the design of a wide variety of controllers. The device is especially
suitable to applications in the communications industry. The IMP is the first device to
offer the benefits of a closely coupled, industry-standard, TS68000/TS68008 micro-
processor core and a flexible communications architecture. This multichannel
communications device may be configured to support a number of popular industry
interfaces, including those for the integrated services digital network (ISDN) basic rate
and terminal adapter applications. Through a combination of architectural and pro-
grammable features, concurrent operation of different protocols is easily achieved
using the IMP. Data concentrators, line cards, bridges, and gateways are examples of
suitable applications for this versatile device.
The IMP is a high-density complementary metal-oxide semiconductor (HCMOS)
device consisting of a TS68000/TS68008 microprocessor core, a system integration
block (SIB), and a communications processor (CP). The TS68302 block diagram is
shown in Figure 1.
Note: GCI is sometimes referred to as IOM2.
Integrated
Multiprotocol
Processor (IMP)
TS68302
Rev. 2117A–HIREL–11/02
1
1 page  
Figure 4. Functional Signal Groups
NMSI1/ISDN I/F
RXD1/L1RXD
TXD1/L1TXD
RCLK1/L1CLK
TCLK1/L1SY0/SDS1
CD1/L1SY1
CTS1/L1RG
RTS1/L1RQ/GCIDCL
BRG1
RXD2/PA0
TXD2/PA1
NMSI2/PIO
RCLK2/PA2
TCLK2/PA3
CTS2/PA4
RTS2/PA5
CD2/PA6
BRG2/SDS2/PA7
NMSI3/SCP/PIO
RXD3/PA8
TXD3/PA9
RCLK3/PA10
TCLK3/PA11
CTS3/SPRXD
RTS3/SPTXD
CD3/SPCLK
BRG3/PA12
DREQ/PA13
DACK/PA14
DONE/PA15
IDMA/PAIO
IACK7/PB0
IACK6/PB1
IACK1/PB2
TIN/PB3
TOUT1/PB4
TIN2/PB5
IACK/PBIO
TIMER/PBIO
TOUT2/ PB6
WDOG/PB7
PBIO (INTERRUPT)
PB8
PB9
PB10
PB11
TS68302
IMP
TS68302
CLOCKS
EXTAL
XTAL
CLKO
ADDRESS BUS
A23-A1
DATA BUS
D15-D0
BUS CONTROL
AS
R/W
UDS/A0
LDS/DS
DTACK
RMC/IOUT1
IAC
BCLR
BUS ARBITRATON
BR
BG
BGACK
SYSTEM CONTROL
RESET
HALT
BERR
BUSW
DISCPU
INTERRUPT CONTROL
IPL0/IRQ1
IPL1/IRQ6
IPL2/IRQ7
FC0
FC1
FC2
AVEC / IOUT0
CHIP SELECT
CS0/IOUT2
CS3-CS1
TESTING
FRZ
NC(2)
GND(13)
VDD(8)
2117A–HIREL–11/02
5
5 Page 
TS68302
Table 6. DC Electrical Characteristics - NMSI1 in IDL mode
Symbol Parameter
Condition
VDD Power
VSS Common
T Temperature
Operating range
Input Pin Characteristics: L1CLK, L1SY1, L1R x D, L1GR
VIL Input Low Level Voltage
VIH Input High Level Voltage
IIH Input Low Level Current
IIH Input High Level Current
Output Pin Characteristics: L1T x D, SDS1-SDS2, L1RQ
(% of VDD)
Vin = VSS
Vin = VDD
VOL Output Low Level Voltage
VOH Output High Level Voltage
IOL = 2.0 mA
IOH = 2.0 mA
Min Nom Max Unit
4.5 5.0
5.5
V
00 0 V
-55 25 +125 °C
-10%
VDD - 20%
+20%
VDD + 10%
±10
±10
V
V
µA
µA
0
VDD - 0.5
0.50
VDD
V
V
2117A–HIREL–11/02
11
11 Page | ||
| Páginas | Total 47 Páginas | |
| PDF Descargar | [ Datasheet TS68302VR16.PDF ] | |
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