TS68C429ADESCxx Datasheet PDF - ATMEL Corporation
| Part Number | TS68C429ADESCxx | |
| Description | CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT | |
| Manufacturers | ATMEL Corporation | |
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Features
• 8 Independent Receivers (Rx)
• 3 Independent Transmitters (Tx)
• Full TS68K Family Microprocessor Interface Compatibility
• 16-bit Data-bus
• ARINC 429 Interface: “1” and “0” Lines, RZ Code
• Support all ARINC 429 Data Rate Transfer and up to 2.5 Mbit/s
• Multi Label Capability
• Parity Control: Odd, Even, No Parity, Interrupt Capability
• Independent Programmable Frequency for Rx and Tx Channels
• 8 Messages FIFO per Tx Channel
• Independent Interrupt Request Line for Rx and Tx Functions
• Vectored Interrupts
• Daisy Chain Capability
• Direct Addressing of all Registers
• Test Modes Capability
• 20 MHz Operating Frequency
• Self-test Capability for Receiver Label Memories and Transmit FiFO
• Low Power: 400 mW
Description
The TS68C429A is an ARINC 429 controller. It is an enhanced version of the EF 4442
and it is designed to be connected to the new 16- or 32-bit microprocessors, espe-
cially these of the Atmel TS68K family.
Screening
• MIL-STD-883, class B
• DESC Drawing 5962-955180
• Atmel Standards
CMOS
ARINC 429
Multichannel
Receiver/
Transmitter
(MRT)
TS68C429A
Application Note
• A detailed application note is available “AN 68C429A” on request.
R suffix
PGA 84
Ceramic Pin Grid Array
F suffix
CQFP 132
Ceramic Quad Flat Pack
Rev. 2120A–HIREL–08/02
1
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TS68C429A
Figure 1. Signal Description (Continued)
Pin Name
Type
Function
RX2L
I Receiving “0” line of the channel 2.
RX3H
I Receiving “1” line of the channel 3.
RX3L
I Receiving “0” line of the channel 3.
RX4H
I Receiving “1” line of the channel 4.
RX4L
I Receiving “0” line of the channel 4.
RX5H
I Receiving “1” line of the channel 5.
RX5L
I Receiving “0” line of the channel 5.
RX6H
I Receiving “1” line of the channel 6.
RX6L
I Receiving “0” line of the channel 6.
RX7H
I Receiving “1” line of the channel 7.
RX7L
I Receiving “0” line of the channel 7.
RX8H
I Receiving “1” line of the channel 8.
RX8L
I Receiving “0” line of the channel 8.
RESET
I This input (active low) will initialize the TS68C429A registers.
VCC/GND
I These inputs supply power to the chip. The VCC is powered at +5 volts and GND is the ground
connection.
CLK-SYS
I The clock input is a single-phase signal used for internal timing of processor interface.
CLK-ARINC
I This input provides the timing clock to synchronize received/transmitted messaged.
2120A–HIREL–08/02
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for TS68C429ADESCxx electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ TS68C429ADESCxx.PDF Datasheet ] | |
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