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TS68C429AVR 데이터시트 PDF




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부품번호 TS68C429AVR 기능
기능 CMOS ARINC 429 Multichannel Receiver/ Transmitter MRT
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TS68C429AVR 데이터시트, 핀배열, 회로
Features
8 Independent Receivers (Rx)
3 Independent Transmitters (Tx)
Full TS68K Family Microprocessor Interface Compatibility
16-bit Data-bus
ARINC 429 Interface: “1” and “0” Lines, RZ Code
Support all ARINC 429 Data Rate Transfer and up to 2.5 Mbit/s
Multi Label Capability
Parity Control: Odd, Even, No Parity, Interrupt Capability
Independent Programmable Frequency for Rx and Tx Channels
8 Messages FIFO per Tx Channel
Independent Interrupt Request Line for Rx and Tx Functions
Vectored Interrupts
Daisy Chain Capability
Direct Addressing of all Registers
Test Modes Capability
20 MHz Operating Frequency
Self-test Capability for Receiver Label Memories and Transmit FiFO
Low Power: 400 mW
Description
The TS68C429A is an ARINC 429 controller. It is an enhanced version of the EF 4442
and it is designed to be connected to the new 16- or 32-bit microprocessors, espe-
cially these of the Atmel TS68K family.
Screening
• MIL-STD-883, class B
• DESC Drawing 5962-955180
Atmel Standards
CMOS
ARINC 429
Multichannel
Receiver/
Transmitter
(MRT)
TS68C429A
Application Note
• A detailed application note is available “AN 68C429A” on request.
R suffix
PGA 84
Ceramic Pin Grid Array
F suffix
CQFP 132
Ceramic Quad Flat Pack
Rev. 2120A–HIREL–08/02
1




TS68C429AVR pdf, 반도체, 판매, 대치품
Package
Figure 1. Signal Description
Pin Name
Type
A0-8
I
D0-15
I/O
CS
LDS
UDS
R/W
DTACK
I
I
I
I
O
IRQTX
IACKTX
IEITX
IEOTX
IRQRX
IACKRX
IEIRX
IEORX
TX1H
TX1L
TX2H
TX2L
TX3H
TX3L
RX1H
RX1L
RX2H
O
I
I
O
O
I
I
I
O
O
O
O
O
O
I
I
I
See “Package Mechanical Data” on page 40 and “Terminal Connections” on page 41.
Function
Address bus. The address bus is used to select one of the internal registers during a processor
read or write cycle.
This bi-directional bus is used to receive data from or transmit data to an internal register during a
processor read or write cycle. During an interrupt acknowledge cycle, the vector number is given
on the lower data bus (D0 - D7).
Chip select (active low). This input is used to select the chip for internal register access.
Lower data strobe. This input (active low) validates lower data during R/W access (D0-D7).
Upper data strobe. This input (active low) validates upper data during R/W access (D8-D15).
Read/write. This input defines a data transfer as a read (high) or a write (low) cycle.
Data transfer acknowledge. If the bus cycle is a processor read, the chip asserts DTACK to
indicate that the information on the data bus is valid. If the bus cycle is a processor write, DTACK
acknowledges the acceptance of the data by the MRT. DTACK will be asserted during chip select
access (CS asserted) or interrupt acknowledge cycle (IACKTX or IACKRK asserted).
Interrupt transmit request. This open drain output signals to the processor that an interrupt is
pending from the transmission part of the MRT. There are 6 causes that can generate an
interrupt request (2 per channel: FIFO empty and end of transmission).
Interrupt transmit acknowledge. If IRQTX is active, the MRT will begin an interrupt acknowledge
cycle. The MRT will generate a vector number to the processor which is the highest priority
channel requesting interrupt service.
Interrupt transmit enable in. This input, together with IEOTX signal, provides a daisy chained
interrupt structure for a vectored scheme. IEITX (active low) indicates that no higher priority
device is requesting interrupt service.
Interrupt transmit enable out. This output, together with IEITX signal, provides a daisy chained
interrupt structure for a vectored interrupt scheme. IEOTX (active low) indicates to lower priority
devices that neither the TS68C429A nor any highest priority peripheral is requesting an interrupt.
Interrupt transmit request. This open drain output signals to the processor that an interrupt is
pending from the receiving part of the chip. There are 9 causes that can generate an interrupt
request (1 per channel: valid message received, and 1 for bad parity on a received message).
Interrupt receive acknowledge. Same function as IACKTX but for receiver part.
Interrupt receive enable in. Same function as IEITX but for receiver part.
Interrupt receive enable out. Same function as IEOTX but for receiver part.
Transmission “1” line of the channel 1.
Transmission “0” line of the channel 1.
Transmission “1” line of the channel 2.
Transmission “0” line of the channel 2.
Transmission “1” line of the channel 3.
Transmission “0” line of the channel 3.
Receiving “1” line of the channel 1.
Receiving “0” line of the channel 1.
Receiving “1” line of the channel 2
4 TS68C429A
2120A–HIREL–08/02

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TS68C429AVR 전자부품, 판매, 대치품
TS68C429A
Design and Construction
Terminal Connections
Depending on the package, the terminal connections is detailed in “Terminal Connec-
tions” on page 41.
Package
The circuits are packaged in a hermetically sealed ceramic package which is conform to
case outlines of MIL-STD 1835 (when defined):
• PGA 84,
• CQFP 132.
The precise case outlines are described at the end of this specification (“Package
Mechanical Data” on page 40) and into MIL-STD-1835.
Special Recommended
Conditions for CMOS Devices
CMOS Latch-up
The CMOS cell is basically composed of two complementary transistors (a P-channel
and an N-channel), and, in the steady state, only one transistor is turned-on. The active
P-channel transistor sources current when the output is a logic high and presents a high
impedance when the output is a logic low. Thus the overall result is extremely low power
consumption because there is no power loss through the active P-channel transistor.
Also since only once transistor is determined by leakage currents.
Because the basic CMOS cell is composed of two complementary transistors, a para-
sitic semiconductor controlled rectifier (SCR) formed and may be triggered when an
input exceeds the supply voltage. The SCR that is formed by this high input causes the
device to become “latched” in a mode that may result in excessive current drain and
eventual destruction of the device. Although the device is implemented with input pro-
tection diodes, care should be exercised to ensure that the maximum input voltages
specification is not exceeded from voltage transients; others may require no additional
circuitry.
CMOS/TTL Levels
The TS68C429A doesn’t satisfy totally the input/output drive requirements of TTL logic
devices, see Table 4.
Electrical Characteristics
Table 1. Absolute Maximum Ratings
Symbol
Parameter
VCC
VI
Pdmax
Supply Voltage
Input Voltage
Max Power Dissipation
Tcase
Operating Temperature
Tstg
Tj
Tleads
Storage Temperature
Junction Temperature
Lead Temperature
Test Conditions
M suffix
V suffix
Max 5 sec. soldering
Min
-0.3
-0.3
-55
-40
-55
Max
+7.0
+7.0
400
+125
+85
+150
+160
+270
Unit
V
V
mW
°C
°C
°C
°C
°C
2120A–HIREL–08/02
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