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TS68EN360DES01MXCL 데이터시트 PDF




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부품번호 TS68EN360DES01MXCL 기능
기능 32-bitQuad Integrated Communication Controller
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TS68EN360DES01MXCL 데이터시트, 핀배열, 회로
Features
CPU32+ Processor (4.5 MIPS at 25 MHz)
– 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32)
– Background Debug Mode
– Byte-misaligned Addressing
Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
Up to 32 Address Lines (At Least 28 Always Available)
Complete Static Design (0 - 25 MHz Operation)
Slave Mode to Disable CPU32+ (Allows Use with External Processors)
– Multiple QUICCs Can Share One System Bus (One Master)
– TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and
Intelligent Peripheral (22 MIPS at 25 MHz)
– Peripheral Device of TSPC603e (see DC415/D note)
Four General-purpose Timers
– Superset of MC68302 Timers
– Four 16-bit Timers or Two 32-bit Timers
– Gate Mode Can Enable/Disable Counting
Two Independent DMAs (IDMAs)
System Integration Module (SIM60)
Communications Processor Module (CPM)
Four Baud Rate Generators
Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full 10 Mbps Support)
Two SMC
VCC = +5V ± 5%
fmax = 25 MHz and 33 MHz
Military Temperature Range: -55°C < TC < +125°C
PD = 1.4 W at 25 MHz; 5.25V
2 W at 33 MHz; 5.25V
32-bit Quad
Integrated
Communication
Controller
TS68EN360
Description
The TS68EN360 QUad Integrated Communication Controller (QUICC) is a versatile
one-chip integrated microprocessor and peripheral combination that can be used in a
variety of controller applications. It particularly excels in communications activities.
The QUICC (pronounced “quick”) can be described as a next-generation TS68302
with higher performance in all areas of device operation, increased flexibility, major
extensions in capability, and higher integration. The term “quad” comes from the fact
that there are four serial communications controllers (SCCs) on the device; however,
there are actually seven serial channels: four SCCs, two serial management control-
lers (SMCs), and one serial peripheral interface (SPI).
Screening/Quality
This product is manufactured in full compliance with:
• MIL-STD-883 (class B)
• QML (class Q)
• or according to Atmel standards
Rev. 2113A–HIREL–03/02
1




TS68EN360DES01MXCL pdf, 반도체, 판매, 대치품
Figure 3. 240-lead Cerquad
GNDs1
CAS3
CAS2
Vcc
CAS1
GND
CAS0
FREEZE
DS
GND
R/W
NC3
Vcc
DSACK0
GND
DSACK1
GND
PRTY3
PRTY2
GND
Vcc
PRTY1
PRTY0
IPIPE0
AS
GNDs2
IPIPE1
Vcc
NC2
BCLRO
GND
OE
IFETCH
NC1
BR
Vcc
GND
BG
BGACK
Vcc
IRQ4
IRQ6
GND
BKPT
RESETH
TRST
TCK
TMS
TDI
TDO
PERR
GND
AVEC
RMC
Vcc
RESETS
HALT
GND
BERR
IRQ1
180
181
190
200
210
220
230
240
1
170 160
PIN ONE INDICATOR
10 20
150 140
TS68EN360
(TOP VIEW)
30 40
130
50
121
120
110
100
90
80
70
61
60
A28
A29
GND
A30
A31
Vcc
SIZ0
SIZ1
FC0
GND
FC1
FC2
FC3
Vcc
GND
D31
D30
D29
GND
D28
D27
D26
Vcc
D25
D24
D23
GND
D22
D21
D20
CLKO1
Vccclk
GNDclk
CLKO2
D19
D18
D17
GND
D16
D15
Vcc
D14
D13
D12
GND
D11
D10
D9
D8
D7
GND
D6
D5
Vcc
D4
D3
D2
GND
D1
D0
4 TS68EN360
2113A–HIREL–03/02

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TS68EN360DES01MXCL 전자부품, 판매, 대치품
TS68EN360
Table 1. System Bus Signal Index (Normal Operation) (Continued)
Group
Signal Name
Mnemonic
Function
Bus Control
Data and Size
Acknowledge
DSACK1 - DSACK0
Provides asynchronous data transfer acknowledgement and
dynamic bus sizing (open-drain I/O but driven high before
three-stated).
Address Strobe
AS Indicates that a valid address is on the address bus. (I/O)
Data Strobe
DS During a read cycle, DS indicates that an external device
should place valid data on the data bus. During a write cycle,
DS indicates that valid data is on the data bus. (I/O)
Size
SIZ1-SIZ0
Indicates the number of bytes remaining to be transferred for
this cycle. (I/O)
Read/Write
R/W
Indicates the direction of data transfer on the bus. (I/O)
Output Enable Address
Multiplex
OE/AMUX
Active during a read cycle indicates that an external device
should place valid data on the data bus (O) or provides a
strobe for external address multiplexing in DRAM accesses
if internal multiplexing is not used. (O)
Interrupt
Control
Interrupt Request
Level 7-1
IRQ7-IRQ1
Provides external interrupt requests to the CPU32+ at
priority levels 7-1. (I)
Autovector/Interrupt
Acknowledge 5
AVEC/IACK5
Autovector request during an interrupt acknowledge cycle
(open-drain I/O) or interrupt level 5 acknowledge line. (O)
System
Control
Soft Reset
Hard Reset
RESETS
RESETH
Soft system reset. (open-drain I/O)
Hard system reset. (open-drain I/O)
Halt
HALT
Suspends external bus activity. (open-drain I/O)
Bus Error
BERR
Indicates an erroneous bus operation is being attempted.
(open-drain I/O)
Clock and Test System Clock Out 1
CLKO1
Internal system clock output 1. (O)
System Clock Out 2
CLKO2
Internal system clock output 2 - normally 2x CLKO1. (O)
Crystal Oscillator
EXTAL, XTAL
Connections for an external crystal to the internal oscillator
circuit. EXTAL (I), XTAL (O).
External Filter Capacitor
XFC
Connection pin for an external capacitor to filter the circuit of
the PLL. (I)
Clock Mode Select 1-0
MODCK1-MODCK0 Selects the source of the internal system clock. (I) THESE
PINS SHOULD NOT BE SET TO 00
Instruction Fetch/
Development Serial Input
IFETCH/DSI
Indicates when the CPU32+ is performing an instruction
word prefetch (O) or input to the CPU32+ background debug
mode. (I)
Instruction Pipe 0/
Development Serial
Output
IPIPE0/DSO
Used to track movement of words through the instruction
pipeline (O) or output from the CPU32+ background debug
mode. (O)
Instruction Pipe 1/Row
Address Select 1
Double-Drive
IPIPE1/RAS1DD
Used to track movement of words through the instruction
pipeline (O), or a row address select 1 “double-drive” output
(O).
Breakpoint/Development
Serial Clock
BKPT/DSCLK
Signals a hardware breakpoint to the QUICC (open-drain
I/O), or clock signal for CPU32+ background debug mode (I).
Freeze/Initial
Configuration 2
FREEZE/CONFIG2 Indicates that the CPU32+ has acknowledged a breakpoint
(O), or initial QUICC configuration select (I).
2113A–HIREL–03/02
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부품번호상세설명 및 기능제조사
TS68EN360DES01MXCL

32-bitQuad Integrated Communication Controller

ATMEL Corporation
ATMEL Corporation

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