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PDF TS68EN360DES02MXCL Data sheet ( Hoja de datos )
| Número de pieza | TS68EN360DES02MXCL | |
| Descripción | 32-bitQuad Integrated Communication Controller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• CPU32+ Processor (4.5 MIPS at 25 MHz)
– 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32)
– Background Debug Mode
– Byte-misaligned Addressing
• Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits)
• Up to 32 Address Lines (At Least 28 Always Available)
• Complete Static Design (0 - 25 MHz Operation)
• Slave Mode to Disable CPU32+ (Allows Use with External Processors)
– Multiple QUICCs Can Share One System Bus (One Master)
– TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and
Intelligent Peripheral (22 MIPS at 25 MHz)
– Peripheral Device of TSPC603e (see DC415/D note)
• Four General-purpose Timers
– Superset of MC68302 Timers
– Four 16-bit Timers or Two 32-bit Timers
– Gate Mode Can Enable/Disable Counting
• Two Independent DMAs (IDMAs)
• System Integration Module (SIM60)
• Communications Processor Module (CPM)
• Four Baud Rate Generators
• Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full 10 Mbps Support)
• Two SMC
• VCC = +5V ± 5%
• fmax = 25 MHz and 33 MHz
• Military Temperature Range: -55°C < TC < +125°C
• PD = 1.4 W at 25 MHz; 5.25V
2 W at 33 MHz; 5.25V
32-bit Quad
Integrated
Communication
Controller
TS68EN360
Description
The TS68EN360 QUad Integrated Communication Controller (QUICC™) is a versatile
one-chip integrated microprocessor and peripheral combination that can be used in a
variety of controller applications. It particularly excels in communications activities.
The QUICC (pronounced “quick”) can be described as a next-generation TS68302
with higher performance in all areas of device operation, increased flexibility, major
extensions in capability, and higher integration. The term “quad” comes from the fact
that there are four serial communications controllers (SCCs) on the device; however,
there are actually seven serial channels: four SCCs, two serial management control-
lers (SMCs), and one serial peripheral interface (SPI).
Screening/Quality
This product is manufactured in full compliance with:
• MIL-STD-883 (class B)
• QML (class Q)
• or according to Atmel standards
Rev. 2113A–HIREL–03/02
1
1 page  
Signal Description
Functional Signal Group
Figure 4. QUICC Functional Signal Groups
PORT A
RXD1/PA0
TXD1/PA1
RXD2/PA2
TXD2/PA3
L1TXDB/RXD3/PA4
L1RXDB/TXD3/PA5
L1TXDA/RXD4/PA6
L1RXDA/TXD4/PA7
TIMERs/SCCs/SIs/CLOCKs/BRG
TIN1/L1RCLKA/BRGO1/CLK1/PA8
BRGCLK1/TOUT1/CLK2/PA9
TIN2/L1TCLKA/BRGO2/CLK3/PA10
TOUT2/CLK4/PA11
TIN3/BRGO3/CLK5/PA12
BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13
TIN4/BRGO4/CLK7/PA14
L1TCLKB/TOUT4/CLK8/PA15
PORT B (PIP)
RRJCT1/SPISEL/PB0
RSTRT2/SPICLK/PB1
RRJCT2/SPIMOSI(SPITXD)/PB2
BRGO4/SPIMISO(SPIRXD)/PB3
DREQ1/BRGO1/PB4
DACK1/BRGO2/PB5
DONE1/SMTXD1/PB6
DONE2/SMRXD1/PB7
DREQ2/SMSYN1/PB8
DACK2/SMSYN2/PB9
L1CLKOB/SMTXD2/PB10
L1CLKOA/SMRXD2/PB11
L1ST1/RTS1/PB12
L1ST2/RTS2/PB13
L1ST3/L1RQB/RTS3/PB14
L1ST4/L1RQA/RTS4/PB15
STRBO/BRGO3/PB16
STRBI/RSTRT1/PB17
PORT C (INTERRUPT PARALLEL I/O)
L1ST1/RTS1/PC0
L1ST2/RTS2/PC1
L1ST3/L1RQB/RTS3/PC2
L1ST4/L1RQA/RTS4/PC3
CTS1/PC4
TGATE1/CD1/PC5
CTS2/PC6
TGATE2/CD2/PC7
SDACK2/L1TSYNCB/CTS3/PC8
L1RSYNCB/CD3/PC9
SDACK1/L1TSYNCA/CTS4/PC10
L1RSYNCA/CD4/PC11
QUICC
TS68360
240 PINS
TS68EN360
ADDRESS BUS
A27±A0
A31±A28/WE0±WE3
FC2±FC0/TM2±TM0
FC3/TT0
DATA BUS
D31±D16
D15±D0
PRTY1±PRTY2/IOUT1±IOUT2
PRTY2/IOUT0/RQOUT
PRTY3/16BM
BUS CONTROL
SIZ0
SIZ1
DSACK0/TBI
DSACK1/TA
R/W
AS
DS/TT1
OE/AMUX
BUS ARBITRATION
RMC/CONFIG0/LOCK
BR
BG
BGACK/BB
BCLRO/CONFIG1/RAS2DD
SYSTEM CONTROL
RESETH
RESETS
HALT
BERR/TEA
PERR
INTERRUPT CONTROL
IRQ1/OUT0/RQOUT
IRQ4/OUT1
IRQ6/OUT2
IRQ2,3,5,7
AVEC/IACK5/AVECO
MEMORY CONTROLLER
CS6±CS0/RAS6±RAS0
CS/RAS7/IACK7
CAS3±CAS0/IACK6,3,2,1
TEST
TRIS/TS
BKPT/BKPT0/DSCLK
FREEZE/CONFIG2/MBARE
IPIPE1/RAS1DD/BCLRI
IPIPE0/BADD2/DSO
IFETCH/BADD3/DSI
TCK
TMS
TDI
TDO
TRST
CLOCK
XTAL
EXTAL
XFC
MODCK1±MODCK0
CLKO2±CLKO1
2113A–HIREL–03/02
5
5 Page 
TS68EN360
Requirements
General
This microcircuits are in accordance with the applicable document and as specified
herein.
Design and Construction
Terminal Connections
Depending on the package, the terminal connections shall be as shown in Figure 2 and
Figure 3.
Lead Material and Finish
Lead material and finish shall be as specified in MIL-STD-883 (see enclosed “Ordering
Information” on page 79).
Package
The macrocircuits are packaged in hermetically sealed ceramic packages which are
conform to case outlines of MIL-STD-1835 or as follow:
• PGA but see “241-pin – PGA” on page 77
• CERQUAD
The precise case outlines are described at the end of the specification (“Package
Mechanical Data” on page 77) and into MIL-STD-1835.
Electrical
Characteristics
Table 3. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply Voltage(1)(2)
Input Voltage(1)(2)
VCC -0.3 to +6.5 V
VIN
-0.3 to +6.5
V
Storage Temperature Range
TSTG
-55 to +150
°C
Note: This device contains protective circuitry against damage due to high static voltages or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-imped-
ance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND
or VDD).
Notes: 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recom-
mended values affects device reliability. Device modules may not operate normally while being exposed to electrical
extremes.
2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take
normal precautions to avoid exposure to voltages higher than maximum-rated voltages.
3. The supply voltage VCC must start and restart from 0.0V; otherwise, the 360 will not come out of reset properly.Unless other-
wise stated, all voltages are referenced to the reference terminal.
2113A–HIREL–03/02
11
11 Page | ||
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| PDF Descargar | [ Datasheet TS68EN360DES02MXCL.PDF ] | |
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