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TS68HC901 데이터시트 PDF




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부품번호 TS68HC901 기능
기능 HCMOS MULTI-FUNCTION PERIPHERAL
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TS68HC901 데이터시트, 핀배열, 회로
® TS68HC901
HCMOS MULTI-FUNCTION PERIPHERAL
The TS68HC901 CMFP (CMOS Multi-Function
Peripheral) is a combination of many of the neces-
sary peripheral functions in a microprocessor sys-
.tem.
Included are :
8 INPUT/OUTPUT PINS
Individually programmable direction
. Individual interrupt source capability
- Programmable edge selection
16 SOURCE INTERRUPT CONTROLLER
8 Internal sources
8 External sources
Individual source enable
Individual source masking
Programmable interrupt service modes
- Polling
- Vector generation
. - Optional In-service status
Daisy chaining capability
FOUR TIMERS WITH INDIVIDUALLY
PROGRAMMABLE PRESCALING
Two multimode timers
- Delay mode
- Pulse width measurement mode
- Event counter mode
Two delay mode timers
. Independent clock input
Time out output option
SINGLE CHANNEL USART
Full Duplex
Asynchronous to 65 kbps
Byte synchronous to 1 Mbps
Internal/External baud rate generation
DMA handshake signals
. Modem control
Loop back mode
68000 BUS COMPATIBLE
DESCRIPTION
The use of the CMFP in a system can significantly
reduce chip count, thereby reducing system cost.
The CMFP is completely 68000 bus compatible, and
24 directly addressable internal registers provide
the necessary control and status interface to the pro-
grammer.
The CMFP is a derivative of the MK3801 STI, a Z80
family peripheral.
September 1992
48
1
PDIP48
PLCC52
(Ordering Information at the end of the Datasheet
1/42




TS68HC901 pdf, 반도체, 판매, 대치품
TS68HC901
Figure 3 : PDIP Pin connection
Figure 4 : PLCC Pin connection
Pin MOTOROLA MOTOROLA
6800 Type Multiplexed
48 CS
47 E
1 R/W
35 VSS
CS
DS
R/W
AS
INTEL
CS
RD
WR
ALE
PIN DESCRIPTION
GND : Ground
VCC : +5 volts (± 5%)
R/W :
Read/Write (input). This input defines a
data transfert as a Read (High) or Write
(Low) cycle. This signal is used as WR
with an Intel processor type.
DTACK : This output signals the completion of the
operation phase of a bus cycle to the pro-
cessor. If the bus cycle is a processor
read, the CMFP asserts DTACK to indi-
cate that the information on the Data bus
is valid. If the bus cycle is a processor to
the CMFP, DTACK acknowledges the
acceptance of the data by the CMFP.
DTACK will be asserted only by an CMFP
that has CS or IAK (and IEI) asserted.
This signal is not used with a 6800 pro-
cessor type.
CS :
DS :
Chip Select (input, active low). CS is u-
sed to select the TS68HC901 CMFP for
accesses to the internal registers. CS
and IACK must not be asserted at the
same time.
Data Stobe (input, active low).This Input
is part of the internal chip select and in-
terrupt acknowledge functions.
The CMFP must be located on the lower
portion of the 16-bit data-bus so that the
vector number passed to the processor
during an interrupt acknowledge cycle
will be located in the low byte of the data
word. As a result, DS must be connected
to the processor’s lower data strobe if
vectored interrupt are to be used. Note
that this forces all registers to be located
at odd addresses and latches data on the
rising edge for writes. This signal is used
as RD with an Intel processor type.
4/42
®

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TS68HC901 전자부품, 판매, 대치품
TS68HC901
BUS OPERATION
The following paragraphs explain the control signals
and bus operation during data transfer operations
and reset.
DATA TRANSFER OPERATIONS.
Transfer of data between devices involves the follo-
wing pins: Register Select Bus - RS5 through RS1
Data Bus - D0 through D7 Control Signals The ad-
dress and data buses are separate parallel buses u-
sed to transfer data using an asynchronous bus
structure. In all cycles, the bus master assumes re-
sponsibility for deskewing all signals it issues at both
the start and end of a cycle. Additionally, the bus
master is responsible for deskewing the acknow-
ledge and data signals from the peripheral devices.
Read Cycle. To read a CMFP register, CS and DS
must be asserted, and R/W must be high. The
CMFP will place the content of the register which is
selected by the register select bus (RS1 through
RS5) on the data bus (D1 through D7) and then as-
sert DTACK. The register addresses are shown on
Figure 2. After the processor has latched the data, DS
is negated. The negation of either CS or DS will ter-
minate the read operation. The CMFP will drive
DTACK High and place it in the high-impedance state.
The timing for a read cycle is shown in figure 21.
Write Cycle. To write a register CS and DS must be
asserted, and R/W must be low. The CMFP will de-
code the address bus to determine which register is
selected. Then the register will be loaded with the
contents of the data bus and DTACK will be asser-
ted. When the processor recognizes DTACK, DS
will be negated. The write cycle is terminated when
either CS or DS is negated. The CMFP will drive
DTACK high and place it in the high-impedance state.
The timing for a write cycle is shown in figure 22.
INTERRUPT ACKNOWLEDGE OPERATION.
The CMFP has 16 interrupt sources, eight internal
and eight external. When an interrupt request is
pending, the CMFP will assert IRQ. In a vectored in-
terrupt scheme, the processor will acknowledge the
interrupt request by performing an interrupt acknow-
ledge cycle. IACK and DS will be asserted. The
CMFP responds to the IACK signal by placing a vec-
tor number on the lower eight bits of the data bus.
This vector number corresponds to the IRQ handler
for the particular interrupt requesting service. The
format of this vector number is given in figure 6.
When the CMFP asserts DTACK to indicate that va-
lid data is on the bus, the processor will latch the da-
ta and terminate the bus cycle by negating DS.
When either DS or IACK are negated, the CMFP will
terminate the interrupt acknowledge operation by
driving DTACK high and placing it in the high-impe-
dance state. Also, the data bus will be placed in the
high-impedance state. IRQ will be negated as a re-
sult of the IACK cycle unless additional interrupts
are pending.
The CMFP can be part of a daisy-chain interrupt
structure which allows multiple CMFPs to be placed
at the same interrupt level by sharing a common
IACK signal. A daisy-chain priority scheme is imple-
mented with IEI and IEO signals. IEI indicates that
no higher priority device is requesting interrupt ser-
vice. IEO signals lower priority devices that neither
this device nor any higher priority devices is reques-
ting service. To daisy-chain CMFPs, the highest
priority CMFP has its IEI tied low and successive
CMFPs have their IEI connected to the next higher
priority device’s IEO. Note that when the daisy-chain
7/42
®

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TS68HC901

HCMOS MULTI-FUNCTION PERIPHERAL

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