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TS80C31X2-MCER PDF 데이터시트 ( Data , Function )

부품번호 TS80C31X2-MCER 기능
기능 8-bit CMOS Microcontroller ROMless
제조업체 ATMEL Corporation
로고 ATMEL Corporation 로고 



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TS80C31X2-MCER 데이터시트, 핀배열, 회로
8-bit CMOS Microcontroller ROMless
TS80C31X2
1. Description
TS80C31X2 is high performance CMOS and ROMless
versions of the 80C51 CMOS single chip 8-bit
microcontroller.
The TS80C31X2 retains all features of the TSC80C31
with 128 bytes of internal RAM, a 5-source, 4 priority
level interrupt system, an on-chip oscilator and two timer/
counters.
In addition, the TS80C31X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C31X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C31X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q 80C31 Compatible
8031 pin and instruction compatible
Four 8-bit I/O ports
Two 16-bit timer/counters
128 bytes scratchpad RAM
q High-Speed Architecture
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
q Dual Data Pointer
q Asynchronous port reset
q Interrupt Structure with
5 Interrupt sources,
4 priority level interrupt system
q Full duplex Enhanced UART
Framing error detection
Automatic address recognition
q Power Control modes
Idle mode
Power-down mode
Power-off Flag
q Once mode (On-chip Emulation)
q Power supply: 4.5-5.5V, 2.7-5.5V
q Temperature ranges: Commercial (0 to 70oC) and
Industrial (-40 to 85oC)
q Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1
(13.9 footprint)
Rev. C - 15 January, 2001
1




TS80C31X2-MCER pdf, 반도체, 판매, 대치품
TS80C31X2
5. Pin Configuration
P1.0 / T2
P1.1 / T2EX
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11 PDIL/
12 CDIL40
13
14
15
16
17
18
19
20
40 VCC
39 P0.0 / A0
38 P0.1 / A1
37 P0.2 / A2
36 P0.3 / A3
35 P0.4 / A4
34 P0.5 / A5
33 P0.6 / A6
32 P0.7 / A7
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7 / A15
27 P2.6 / A14
26 P2.5 / A13
25 P2.4 / A12
24 P2.3 / A11
23 P2.2 / A10
22 P2.1 / A9
21 P2.0 / A8
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12
PLCC44
34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6 PQFP44
7 VQFP44
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
*NIC: No Internal Connection
4 Rev. C - 15 January, 2001

4페이지










TS80C31X2-MCER 전자부품, 판매, 대치품
TS80C31X2
XTAL1
XTAL1:2
X2 bit
CPU clock
STD Mode
X2 Mode
STD Mode
Figure 2. Mode Switching Waveforms
The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles per instruction to 6 clock
cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature
(X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals
using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example
a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with
4800 baud rate will have 9600 baud rate.
Rev. C - 15 January, 2001
7

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