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PDF TS80C31X2-VLAB Data sheet ( Hoja de datos )
| Número de pieza | TS80C31X2-VLAB | |
| Descripción | 8-bit CMOS Microcontroller ROMless | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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8-bit CMOS Microcontroller ROMless
TS80C31X2
1. Description
TS80C31X2 is high performance CMOS and ROMless
versions of the 80C51 CMOS single chip 8-bit
microcontroller.
The TS80C31X2 retains all features of the TSC80C31
with 128 bytes of internal RAM, a 5-source, 4 priority
level interrupt system, an on-chip oscilator and two timer/
counters.
In addition, the TS80C31X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C31X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C31X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q 80C31 Compatible
• 8031 pin and instruction compatible
• Four 8-bit I/O ports
• Two 16-bit timer/counters
• 128 bytes scratchpad RAM
q High-Speed Architecture
• 40 MHz @ 5V, 30MHz @ 3V
• X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
q Dual Data Pointer
q Asynchronous port reset
q Interrupt Structure with
• 5 Interrupt sources,
• 4 priority level interrupt system
q Full duplex Enhanced UART
• Framing error detection
• Automatic address recognition
q Power Control modes
• Idle mode
• Power-down mode
• Power-off Flag
q Once mode (On-chip Emulation)
q Power supply: 4.5-5.5V, 2.7-5.5V
q Temperature ranges: Commercial (0 to 70oC) and
Industrial (-40 to 85oC)
q Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1
(13.9 footprint)
Rev. C - 15 January, 2001
1
1 page  
TS80C31X2
Table 2. Pin Description for 40/44 pin packages
PIN NUMBER
MNEMONIC
TYPE
DIL LCC VQFP 1.4
NAME AND FUNCTION
VSS
Vss1
VCC
P0.0-P0.7
P1.0-P1.7
P2.0-P2.7
P3.0-P3.7
Reset
ALE
PSEN
EA
XTAL1
XTAL2
20 22
1
40 44
39-32 43-36
16
39
38
37-30
1-8 2-9
40-44
1-3
21-28 24-31 18-25
10-17 11,
13-19
5,
7-13
10 11
11 13
12 14
13 15
14 16
15 17
16 18
17 19
9 10
30 33
5
7
8
9
10
11
12
13
4
27
29 32
26
31 35
19 21
18 20
29
15
14
I
I
I
I/O
I/O
I/O
I/O
I
O
I
I
I
I
O
O
I
O (I)
O
I
I
O
Ground: 0V reference
Optional Ground: Contact the Sales Office for ground connection.
Power Supply: This is the power supply voltage for normal, idle and power-
down operation
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s.
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups.
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Port 3 also serves the special
features of the 80C51 family, as listed below.
RXD (P3.0): Serial input port
TXD (P3.1): Serial output port
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VCC.
Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used
for external timing or clocking. Note that one ALE pulse is skipped during each
access to external data memory.
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
External Access Enable: EA must be externally held low to enable the device
to fetch code from external program memory locations.
Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
Crystal 2: Output from the inverting oscillator amplifier
Rev. C - 15 January, 2001
5
5 Page 
ASSEMBLY LANGUAGE
TS80C31X2
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2
AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE
0003 05A2 INC AUXR1
0005 90A000 MOV DPTR,#DEST
0008
LOOP:
0008 05A2 INC AUXR1
000A E0 MOVX A,@DPTR
000B A3 INC DPTR
000C 05A2 INC AUXR1
000E F0 MOVX @DPTR,A
000F A3 INC DPTR
0010 70F6 JNZ LOOP
0012 05A2 INC AUXR1
; address of SOURCE
; switch data pointers
; address of DEST
; switch data pointers
; get a byte from SOURCE
; increment SOURCE address
; switch data pointers
; write the byte to DEST
; increment DEST address
; check for 0 terminator
; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However,
note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.
In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence
matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the
opposite state.
Rev. C - 15 January, 2001
11
11 Page | ||
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