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PDF TS80C32X2-MCAB Data sheet ( Hoja de datos )
| Número de pieza | TS80C32X2-MCAB | |
| Descripción | 8-bit CMOS Microcontroller 0-60 MHz | |
| Fabricantes | TEMIC Semiconductors | |
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8-bit CMOS Microcontroller 0-60 MHz
TS80C52X2
1. Description
TEMIC TS80C52X2 is high performance CMOS ROM,
OTP, EPROM and ROMless versions of the 80C51
CMOS single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the TEMIC
80C51 with extended ROM/EPROM capacity (8
Kbytes), 256 bytes of internal RAM, a 6-source , 4-level
interrupt system, an on-chip oscilator and three timer/
counters.
In addition, the TS80C52X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C52X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C52X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q 80C52 Compatible
• 8051 pin and instruction compatible
• Four 8-bit I/O ports
• Three 16-bit timer/counters
• 256 bytes scratchpad RAM
q High-Speed Architecture
• 40 MHz @ 5V, 30MHz @ 3V
• X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
q Dual Data Pointer
q On-chip ROM/EPROM (8K-bytes)
q Programmable Clock Out and Up/Down Timer/
Counter 2
q Asynchronous port reset
q Interrupt Structure with
• 6 Interrupt sources,
• 4 level priority interrupt system
q Full duplex Enhanced UART
• Framing error detection
• Automatic address recognition
q Low EMI (inhibit ALE)
q Power Control modes
• Idle mode
• Power-down mode
• Power-off Flag
q Once mode (On-chip Emulation)
q Power supply: 4.5-5V, 2.7-5.5V
q Temperature ranges: Commercial (0 to 70oC) and
Industrial (-40 to 85oC)
q Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1
(13.9 footprint), CQPJ44 (window), CDIL40
(window)
Rev. B - Jan. 25, 1999
Preliminary
1
1 page  
TS80C52X2
Table 3. Pin Description for 40/44 pin packages
PIN NUMBER
MNEMONIC
TYPE
DIL LCC VQFP 1.4
NAME AND FUNCTION
VSS
Vss1
VCC
P0.0-P0.7
P1.0-P1.7
P2.0-P2.7
P3.0-P3.7
Reset
20 22
1
40 44
39-32 43-36
16
39
38
37-30
1-8 2-9
40-44
1-3
1
2
21-28
2
3
24-31
40
41
18-25
10-17 11,
13-19
5,
7-13
10 11
11 13
12 14
13 15
14 16
15 17
16 18
17 19
9 10
5
7
8
9
10
11
12
13
4
I Ground: 0V reference
I Optional Ground: Contact the Sales Office for ground connection.
I
Power Supply: This is the power supply voltage for normal, idle and power-
down operation
I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs.Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program verification during
which P0 outputs the code bytes.
I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups. Port 1 also receives the low-order
address byte during memory programming and verification.
Alternate functions for Port 1 include:
I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout
I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during EPROM programming
and verification:
P2.0 to P2.4
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Port 3 also serves the special
features of the 80C51 family, as listed below.
I RXD (P3.0): Serial input port
O TXD (P3.1): Serial output port
I INT0 (P3.2): External interrupt 0
I INT1 (P3.3): External interrupt 1
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
I Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to VSS permits a power-on reset
using only an external capacitor to VCC.
Rev. B - Jan. 25, 1999
Preliminary
5
5 Page 
TS80C52X2
Table 5. AUXR1: Auxiliary Register 1
765432
------
Bit
Number
7
Bit
Mnemonic
Description
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
0 DPS Clear to select DPTR0.
Set to select DPTR1.
Reset Value = XXXX XXX0
Not bit addressable
10
- DPS
Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.
Rev. B - Jan. 25, 1999
Preliminary
11
11 Page | ||
| Páginas | Total 54 Páginas | |
| PDF Descargar | [ Datasheet TS80C32X2-MCAB.PDF ] | |
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