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TS80C32X2-MICB PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 TS80C32X2-MICB
기능 8-bit CMOS Microcontroller 0-60 MHz
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TS80C32X2-MICB 데이터시트, 핀배열, 회로
8-bit CMOS Microcontroller 0-60 MHz
TS80C52X2
1. Description
TEMIC TS80C52X2 is high performance CMOS ROM,
OTP, EPROM and ROMless versions of the 80C51
CMOS single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the TEMIC
80C51 with extended ROM/EPROM capacity (8
Kbytes), 256 bytes of internal RAM, a 6-source , 4-level
interrupt system, an on-chip oscilator and three timer/
counters.
In addition, the TS80C52X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C52X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C52X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q 80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
q High-Speed Architecture
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
q Dual Data Pointer
q On-chip ROM/EPROM (8K-bytes)
q Programmable Clock Out and Up/Down Timer/
Counter 2
q Asynchronous port reset
q Interrupt Structure with
6 Interrupt sources,
4 level priority interrupt system
q Full duplex Enhanced UART
Framing error detection
Automatic address recognition
q Low EMI (inhibit ALE)
q Power Control modes
Idle mode
Power-down mode
Power-off Flag
q Once mode (On-chip Emulation)
q Power supply: 4.5-5V, 2.7-5.5V
q Temperature ranges: Commercial (0 to 70oC) and
Industrial (-40 to 85oC)
q Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1
(13.9 footprint), CQPJ44 (window), CDIL40
(window)
Rev. B - Jan. 25, 1999
Preliminary
1




TS80C32X2-MICB pdf, 반도체, 판매, 대치품
TS80C52X2
5. Pin Configuration
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
8
9
10
11 PDIL/
12 CDIL40
13
14
15
16
17
18
19
20
40 VCC
39 P0.0
38 P0.1
37 P0.2
36 P0.3
35 P0.4
34 P0.5
33 P0.6
32 P0.7
31 EA/VPP
30 ALE/PROG
29 PSEN
28 P2.7
27 P2.6
26 P2.5
25 P2.4
24 P2.3
23 P2.2
22 P2.1
21 P2.0
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
6 5 4 3 2 1 44 43 42 41 40
7
8
9
10
11
12 PLCC/CQPJ 44
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18 19 20 21 22 23 24 25 26 27 28
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
P1.5
P1.6
P1.7
RST
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
44 43 42 41 40 39 38 37 36 35 34
1
2
3
4
5
6 PQFP44
7 VQFP44
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
NIC*
ALE/PROG
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
*NIC: No Internal Connection
4 Rev. B - Jan. 25, 1999
Preliminary

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TS80C32X2-MICB 전자부품, 판매, 대치품
TS80C52X2
6. TS80C52X2 Enhanced Features
In comparison to the original 80C52, the TS80C52X2 implements some new features, which are:
The X2 option.
The Dual Data Pointer.
The 4 level interrupt priority system.
The power-off flag.
The ONCE mode.
The ALE disabling.
Some enhanced features are also located in the UART and the timer 2.
6.1 X2 Feature
The TS80C52X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following
advantages:
q Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
q Save power consumption while keeping same CPU power (oscillator power saving).
q Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
q Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.
6.1.1 Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.
XTAL1
FXTAL
2
XTAL1:2
0
1
X2
FOSC
CKCON reg
state machine: 6 clock cycles.
CPU control
Figure 1. Clock Generation Diagram
Rev. B - Jan. 25, 1999
Preliminary
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부품번호상세설명 및 기능제조사
TS80C32X2-MICB

8-bit CMOS Microcontroller 0-60 MHz

TEMIC Semiconductors
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TS80C32X2-MICD

8-bit CMOS Microcontroller 0-60 MHz

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