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PDF TMXF28155 Data sheet ( Hoja de datos )
| Número de pieza | TMXF28155 | |
| Descripción | TMXF28155 Super Mapper 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 | |
| Fabricantes | Agere Systems | |
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Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
1 Features
s Versatile IC supports 155/51 Mbits/s SONET/SDH
interface solutions for T3/E3, DS2, T1/E1/J1, and
DS0/E0/J0 applications.
s Implementation supports both linear (1 + 1, unpro-
tected) and ring (UPSR) network topologies.
s Provides full termination of up to 21 E1, 28 T1, or
28 J1.
s Low power 3.3 V supply.
s –40 °C to +85 °C industrial temperature range.
s 456-pin ball grid array (PBGA) package.
s Complies with Bellcore*, ITU, ANSI †, ETSI and Jap-
anese TTC standards: GR-253-CORE, GR-499,
(ATT) TR-62411, ITU-T G.707, G.704, G.706, G.783,
G.962, G.964, G.965, Q.542, T1.105, JT-G704,
JT-G706, JT-G707, JT-I431-a, ETS 300 417-1-1,
ETS 300 011, T1.107, T1.404.
1.1 SONET/SDH Interface
s Termination of a single 155 Mbits/s STS-3/STM-1 or
single 51 Mbits/s STS-1/STM-0.
s Built-in clock and data recovery circuit at
155 Mbits/s STS-3/STM-1 interface (can be dese-
lected if external clock recovery is provided).
s Supports overhead processing for all transport and
path overhead bytes.
s Optional insertion and extraction of overhead bytes
via a serial transport overhead access channel. Con-
figurable as dedicated DCC channels.
s Software controlled linear 1 + 1 protection via dedi-
cated interface to protection card.
s Full path termination and SPE extraction/insertion.
s SONET/SDH compliant condition and alarm report-
ing.
s Built-in diagnostic loopback modes.
s 8 kHz line frame sync output.
* Bellcore is now Telcordia Technologies. Telcordia Technologies is a
trademark of Telcordia Technologies, Inc.
† ANSI is a registered trademark of American National Standards
Institute, Inc.
1.2 STS/STM Pointer Interpreter
s Interprets STS/AU/TU-3 pointers.
s Synchronizes 8 kHz frame and 2 kHz superframe to
system/shelf timing reference by setting the transmit
STS-3/STM-1 pointers to a fixed value of 522.
s Monitors/terminates SPE path overhead.
1.3 Telecom Bus Interface
s Telecom bus interface to mate devices including
clock, data[8], parity, SPE-, J0-, J1-, and V1 timing
indicator.
s Line and path RDI and REI signals passed to mate
devices.
s Three Super Mapper devices, two configured as
mate devices, provide full termination of an
STS-3/STM-1. A three-chip solution to terminate
84 DS1s/J1s or 63 E1s.
1.4 VT Termination/Generation (x28/x21)
s Monitors/terminates VT path overhead for
28 VT1.5/TU-11 or 21 VT2/TU-12.
s Synchronizes VT/TU SPE to system/shelf timing ref-
erence by setting the transmit VT/TU pointers to fixed
values for asynchronous mapping or by dynamically
changing the transmit VT/TU pointers for byte syn-
chronous mapping.
s Fixed pointer generation in transmit side for asyn-
chronous mapping.
s Dynamic pointer generation in transmit side for byte-
synchronous mapping.
1.5 Mapping/Multiplexing Modes (x28/x21)
s Maps DS3 clear channel or framed signal into STS-1
or TUG-3.
s Maps T1/E1/J1 into VT/TU (including DS1 into
TU-12).
s Supports asynchronous, byte-synchronous, and bit-
synchronous mapping.
1 page  
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
2 Preface
Product Description
Table of Contents
Contents
Page
1 Features ............................................................................................................................................................... 1
1.1 SONET/SDH Interface ................................................................................................................................... 1
1.2 STS/STM Pointer Interpreter ......................................................................................................................... 1
1.3 Telecom Bus Interface ................................................................................................................................... 1
1.4 VT Termination/Generation (x28/x21) ............................................................................................................ 1
1.5 Mapping/Multiplexing Modes (x28/x21) ......................................................................................................... 1
1.6 M13 Features ................................................................................................................................................. 2
1.7 DS3/DS2/DS1/E1 Cross Connect .................................................................................................................. 2
1.8 Jitter Attenuation ............................................................................................................................................ 2
1.9 PDH Interfaces ............................................................................................................................................... 2
1.10 T1/E1/J1 Framing Features (x28/x21) ......................................................................................................... 2
1.11 System Test and Maintenance .................................................................................................................... 3
2 Preface ................................................................................................................................................................. 5
2.1 Major Categories ............................................................................................................................................ 6
2.2 Naming Convention for Registers and Parameters ....................................................................................... 6
2.3 Overview ........................................................................................................................................................ 7
Figures
Page
Figure 1. Functional Diagram of Super Mapper ....................................................................................................... 7
Agere Systems Inc.
5
5 Page 
Preliminary Data Sheet
May 2001
TMXF28155 Super Mapper
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information (continued)
Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)
Pin Signal Name
R23 LINETXCLK28
R24 LINETXCLK29
R25 LINETXDATA28
R26 LINETXSYNC29
T1 VSS
T2 RLSDATA4
T3 RLSDATA3
T4 RLSDATA5
T5 VDD
T11 VSS
T12 VSS
T13 VSS
T14 VSS
T15 VSS
T16 VSS
T22 VDD
T23 LINETXDATA29
T24 RSTN
T25 PMRST
T26 VSS
U1 VDD
U2 RLSDATA1
U3 RLSDATA0
U4 RLSDATA2
U5 TDI
U22 PHASEDETDOWN
U23 DTN
U24 PAR1
U25 PAR0
U26 VDD
V1 RLSSPE
V2 RLSPAR
V3 RLSJ0J1V1
V4 RLSCLK
V5 TDO
V22 PHASEDETUP
V23 DATA0
V24 DATA3
V25 DATA1
V26 DATA2
W1 TLSDATA6
W2 TLSDATA7
W3 TLSDATA5
W4 RLSV1
Agere Systems Inc.
Pin Signal Name
W5 TMSN
W22
TXDATAEN
W23
DATA4
W24
DATA7
W25
DATA5
W26
DATA6
Y1 TLSDATA2
Y2 TLSDATA3
Y3 TLSDATA1
Y4 TLSDATA4
Y5 VSS
Y22 VSS
Y23 DATA8
Y24 DATA11
Y25 DATA9
Y26 DATA10
AA1
VSS
AA2 TLSCLK
AA3 TLSPAR
AA4 TLSDATA0
AA5 RTOACSYNC
AA22
ADDR13
AA23
DATA12
AA24
DATA14
AA25
DATA13
AA26
VSS
AB1
VDD
AB2 TLSSPE
AB3 TLSV1
AB4 TLSJ0J1V1
AB5
VDD
AB6 TTOACCLK
AB7
VSS
AB8 TRSTN
AB9 IC3STATEN
AB10
CTAPRH
AB11
VDD
AB12
VSSA_CDR
AB13
CTAPRP
AB14 LOPOHVALIDIN
AB15 LOPOHCLKOUT
AB16
VDD
AB17 LOPOHDATAOUT
AB18 LOPOHVALIDOUT
Pin
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
Signal Name
RXDATAEN
VDD
MODE2_PLL
VDD
ADDR19
INTN
DATA15
VDD
RLSSYNC52
RLSC52
TLSC52
VSS
TPOACSYNC
AUTO_AIS1
RHSCP
THSSYNCP
VDDA_CDR
RPSC155P
REF10
TPSC155P
LOPOHCLKIN
LOPOHDATAIN
ETOGGLE
TSTMUX0
E1XCLK
CSN
ADDR0
ADDR4
ADDR8
ADDR12
VSS
ADDR17
APS_INTN
ADDR18
RTOACCLK
TLSSYNC52
RTOACDATA
RPOACDATA
TPOACDATA
AUTO_AIS3
RHSFSYNCN
RHSCN
THSSYNCN
RPSD155P
Pin
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
AF1
AF2
Signal Name
RPSC155N
REF14
TPSC155N
ECSEL
TSTSFTLD
DS1XCLK
MPMODE
DSN
ADDR3
ADDR7
ADDR10
VDDD_PLL
VSSS_PLL
CLKIN_PLL
ADDR16
ADDR15
VSS
TTOACDATA
RPOACCLK
TPOACCLK
LOSEXT
AUTO_AIS2
RHSDN
THSCN
THSDN
RPSD155N
CTAPTH
RESLO
TPSD155N
BYPASS
EXDNUP
TSTMUX1
MPCLK
ADSN
ADDR1
ADDR5
ADDR9
ADDR11
VDDS_PLL
MODE1_PLL
ADDR14
VSS
VDD
VSS
11
11 Page | ||
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| PDF Descargar | [ Datasheet TMXF28155.PDF ] | |
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