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PDF TLP558 Data sheet ( Hoja de datos )
| Número de pieza | TLP558 | |
| Descripción | Isolated Bus Driver High Speed Line Receiver Microprocessor System Interfaces MOS FET Gate Driver Transistor Inverter | |
| Fabricantes | Toshiba Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de TLP558 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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TOSHIBA Photocoupler GaAℓAs IRed & Photo IC
TLP558
TLP558
Isolated Bus Driver
High Speed Line Receiver
Microprocessor System Interfaces
MOS FET Gate Driver
Transistor Inverter
Unit in mm
The TOSHIBA TLP558 consisits of a GaAℓAs light emitting diode and
integrated high gain, high speed photodetector.
This unit is 8−lead DIP package.
The detector has a three state output stage that provides source drive
and sink drive, and built−in schmitt trigger. The detector IC has an
internal shield that provides a guaranteed common mode transient
immunity of 1000V / µs. TLP558 is inverter logic type. For buffer logic
type, TLP555 is in line−up.
l Input current: IF=1.6mA(max.)
l Power supply voltage: VCC=4.5~20V
l Switching speed: tpHL, tpLH=400ns(max.)
l Common mode transient immunity: ±1000V /
µs(min.)
l Guaranteed performance over temperature:
−25~85°C
l Isolation voltage: 2500Vrms(min.)
l UL recognized: UL1577, file No. E67349
Truth Table(positive logic)
Input
Enable
Output
HH L
L HH
HLZ
LLZ
A 0.1µF bypass capacitor must be connected
between pins 8 and 5 (see Note 9).
TOSHIBA
Weight: 0.54 g
11−10C4
Pin Configuration(top view)
1
VCC
8 1 : NC
2 : Anode
2 7 3 : Cathode
4 : NC
3 6 5 : GND
4
GND
Shield
6 : VO(Output)
5 7 : VE(Enable)
8 : VCC
Schematic
IE
VE
ICC 7
VCC
8
+
VF 2
-
3
IF
Shield
IO
VO
6
GND
5
1 2002-09-25
1 page  
TLP558
(Note 6) Duration of output short circuit time should not exceed 10ms.
(Note 7) The tpLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the
1.3V point on the leading edge of the output pulse. The tpHL propagation delay is measured from the 50%
point on the leading edge of the input pulse to the 1.3V point on the trailing edge of the output pulse.
(Note 8) CML is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage
in the logic low state (VO > 0.8V).
CMH is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage
in the logic state (VO > 2.0).
(Note 9) A ceramic capacitor (0.1µF) should be connected from pin 8 to pin 5 to stabilize the operation of the high
gain linear amplifier. Failure to provide the bypassing may impair the switching property. The total lead length
between capacitor and coupler should not exceed 1cm.
Test Circuit 1: tpLH, tpHL, tr And tf
Input IF
Output VO
tpHL
90%
10%
tf
IF(ON)
50%
0mA
tpLH
1.3V
VOH
t r VOL
Pulse generation
tr = tf = 5ns
VO = 5V
VCC
VO Monitor
5V
IF
IF Monitor
1
2
3
4
VCC 8
7
6
GND 5
CL
D1～D4
D1 : 1S1588
D2
D3
D4
CL is approximately 15pF which includes
probe and stray wiring capacitance.
5 2002-09-25
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet TLP558.PDF ] | |
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