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TK75020 데이터시트 PDF




TOKO에서 제조한 전자 부품 TK75020은 전자 산업 및 응용 분야에서
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부품번호 TK75020 기능
기능 ZVS RESONANT CONTROLLER
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TK75020 데이터시트, 핀배열, 회로
TK75020
ZVS RESONANT CONTROLLER
FEATURES
s Optimized for Off-Line and Battery Powered
Operation
s Internal Zero-Voltage Detector
s Soft-Start
s Pulse-by-Pulse Current Limit
s Overdissipation Protection with Soft-Start
s Overvoltage Protection with Soft-Start
s Low-Current Standby mode
s Programmable On/Off Timing
s Enable Control
APPLICATIONS
s Cold Cathode Fluorescent Lamps
s Resonant Power Supplies
s Power Supplies for Notebook Computers
s Power Supplies for Personal Electronics
DESCRIPTION
The TK75020 is a low-cost, high-performance Zero-Voltage
Switching (ZVS) controller IC. The primary applications
are in inverters for Cold Cathode Fluorescent Lamps
(CCFL) and in ZVS quasi-resonant or multi-resonant
converters. The combination of a unique (patent-pending)
control concept and a ZVS resonant inverter generates
low-distortion sine wave for the fluorescent lamp, leading
to extended lamp life and high luminous efficiency. The IC
features all necessary circuits of a controller for such
applications, including externally adjustable timing
parameters (frequency, Ton(min), Toff(max)), current limit,
Soft-Start, enable, error amplifier, and a trimmed reference.
The same reference is used for undervoltage protection
and other critical internal biases. Supply current in the “off”
mode is kept at a minimum level (2 µA typical). Special
care has been taken to avoid undesirable turn-on of the
external power MOSFET when sufficient supply voltage is
not available, or when the device is held in the off mode.
Even with no Vcc applied, the drive pin of the IC will sink in
excess of 20 mA while maintaining the voltage below 1 V
to prevent that leakage currents turn on the power MOSFET.
An internal zero-voltage detector monitors the voltage
across the MOSFET and ensures that the turn-on will only
take place under zero-voltage conditions. A unique
overdissipation protection prevents the overheating of the
power MOSFET in case the zero-voltage switching is lost.
The TK75020 is available in a 14-lead surface mount
package.
TK75020
ORDERING INFORMATION
TK75020
Tape/Reel Code
TAPE/REEL CODE
TL: Tape Left
75020
DRV
GND
OVP
EN
CT
TOFF(MAX)
TON/SS
VCC
Vref
CL
ZVD
EAOUT
EAINV
ODP
January 1999 TOKO, Inc.
Page 1




TK75020 pdf, 반도체, 판매, 대치품
TK75020
TK75020 ELECTRICAL CHARACTERISTICS (CONT.)
Test conditions: VCC = 12 V, VEN = 2.4 V, CT = 360 pF, ITON / SS = ITOFF(MAX) = 50 µA, DRV is Open, TA = Full Operating
Temperature Range, Typical numbers apply at TA = 25 °C, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MAXIMUM OFF-TIME SETTING SECTION (TOFF(MAX) PIN)
IT(OFF, MAX)
Short Circuit Current
VT(OFF, MAX) = 0 V
VT(OFF, MAX)
Pin Voltage
IT(OFF, MAX) = 0 mA
TIMING SECTION (CT PIN)
VCT(LOW)
Low Threshold Voltage
VCT(HIGH)
High Threshold Voltage
f Oscillator Frequency
CTRTON
Current Transfer Ratio to CT Pin,
On-time Setting
VCT = 4 V
CTRTOFF(MAX)
Current Transfer Ratio to CT Pin,
Max Off-time Setting
VCT = 0 V
ZERO VOLTAGE DETECTOR SECTION (ZVD PIN)
VZVD(TH)
Detector Low Threshold
TA = 25 ° C
IZVD Input Current
VZVD = 2 V
tZVD(DRV)
Delay to DRV
VZVD Steps From 5 to 0 V,
CDRV = 1 nF
OVERDISSIPATION DETECTOR SECTION (ODP PIN)
VODP(TH)
Detection Threshold Volage
IODP(AVG)
Average Current
f = 100 kHz, TOVERLAP = 200 ns
OVERVOLTAGE DETECTOR SECTION (OVP PIN)
VOVP(TH)
tOVP(D)
Detection Threshold Volage
Dealy to DRV
MIN
1.8
0.9
2.7
115
-6.2
4.75
1.8
-50
0.45
3.6
TYP
2.5
2.0
1.0
3.0
140
-5.5
5.25
2.0
170
0.70
0.6
4.0
350
MAX UNITS
mA
2.2 V
1.1 V
3.3 V
165 kHz
-4.8
5.75
2.2 V
0 µA
300 ns
0.95
V
µA
4.3 V
800 ns
Page 4
January 1999 TOKO, Inc.

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TK75020 전자부품, 판매, 대치품
TK75020
PIN DESCRIPTION (CONT.)
the DRV pin is held low. The drive latch may be set either
by the output of comparator CMP3 through the two-input
OR gate G2 or by the ZVD comparator through G1 and G2.
CMP3 detects if the timing voltage reached 3 V, the ZVD
comparator detects if the voltage at the ZVD pin dropped
below 2 V. Note that gate G1 allows setting the drive latch
through the ZVD pin only when the voltage at the CT pin is
higher than 1.5 V and the current limit latch is in the reset
state. The reason for disabling the ZVD path at CT pin
voltages lower than 1.5 V is to prevent an immediate turn-
on of the MOSFET after it was turned off. CMP4 is used to
detect if the CT pin voltage is higher than 1.5 V.
When the voltage of the timing capacitor is falling (due to
the discharging current set by the external resistors between
the output of the error amplifier and the TON/SS pin, as well
as between the TON/SS pin and ground), the DRV pin is
allowed to go high. The charge and discharge currents are
enabled exclusively.
ZERO VOLTAGE DETECTION PIN (ZVD)
This pin is connected to the drain of the power MOSFET
switch of the converter or inverter through a high value
resistor or a diode. When the MOSFET is turned off, the
drain voltage increases at first and then decreases, due to
the resonant action in the loading network of the switch.
When the drain voltage is above the supply voltage of the
IC, the ZVD pin voltage is clamped to the supply voltage
through the internal diode D1. As the drain voltage drops
below the supply voltage, the voltage of the ZVD pin begins
to follow it. When the ZVD pin voltage drops below 2 V, the
output of the ZVD comparator goes high and sets the drive
latch through gates G1 and G2. Unless there is a fault
condition, the DRV pin goes high and turns on the MOSFET
switch. By having the ZVD feature, the circuit automatically
sets the optimum off time, essentially independently from
the value of the resistor between the TOFF(MAX) pin and
ground.
ERROR AMPLIFIER PIN (EAOUT)
The EAOUT pin is the output of the internal error amplifier.
The output stage of the amplifier is an open-collector
transistor. It is normally connected to the TON/SS pin via an
external resistor. The non-inverting input of the error
amplifier is internally tied to a trimmed 1.25 V reference.
The error amplifier is short-circuit protected.
ERROR AMPLIFIER INPUT PIN (EAINV)
The EAINV pin (the inverting input of the error amplifier)
serves for receiving either an external voltage-feedback or
an external current-feedback signal. The compensating
network of the feedback loop is usually connected between
the EAINV and the EAOUT pins.
TURN-ON TIMING / SOFT-START PIN (TON / SS)
The on-time is inversely proportional to the current flowing
in the resistor connected between this pin and the EAOUT
pin. The TON/SS pin is also useful for providing Soft-Start
at turn-on. Soft-Start can be achieved by connecting the
series combination of a resistor and capacitor between the
TON/SS pin and ground. When the normal operation of the
IC is enabled (either because the VCC voltage exceeds the
upper UVLO threshold or because the IC is turned on by
the Enable pin), the Soft-Start capacitor, which was initially
discharged, begins to charge up through the series resistor.
The charging current adds to the current flowing in the on-
time-setting resistor and sets a shorter on time. As the
voltage builds up across the soft-start capacitor the charging
current gradually decreases and the on time gradually
increases.
At normal operation a voltage-to-current converter formed
by A2 and Q2 keeps the voltage of the TON/SS pin at 2 V.
The current flowing through R2 and the external resistor
connected to the TON/SS pin and ground is mirrored with
Q3 and Q4 into a second mirror formed by Q5 and Q6. The
diode-connected section of the second mirror is shorted
with the transistor Q7 via Q8 when the current switch latch
is reset.
MAXIMUM TURNOFF TIMING PIN (TOFF(MAX))
An external resistor connected between this pin and ground
sets the current that charges the timing capacitor. The
maximum possible off time is inversely proportional to the
value of that current. As discussed previously, when the off
period is terminated by the zero-voltage detector, the
actual off time becomes shorter than the value set by this
resistor.
At normal operation the voltage of the TOFF (MAX) pin is kept
at 2 V with the help of a voltage-to-current converter
formed by the amplifier A1 and transistor Q1. The current
flowing through the off time setting resistor and R1 is
January 1999 TOKO, Inc.
Page 7

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