TJA1010T Datasheet PDF - NXP Semiconductors
| Part Number | TJA1010T | |
| Description | Octal Low Side Driver OLSD | |
| Manufacturers | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
TJA1010
Octal Low Side Driver (OLSD)
Preliminary specification
File under Integrated Circuits, IC18
1998 Feb 09
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Philips Semiconductors
Octal Low Side Driver (OLSD)
Preliminary specification
TJA1010
FUNCTIONAL DESCRIPTION (see Figs 1, 3 and 4)
This octal low side driver is intended to drive relays in
automotive applications. It is optimized to withstand the
wide temperature and supply voltage range that is typical
for this application area. It consists of 8 protected outputs,
including diagnostic functions, controlled by a serial
interface. These outputs can be used in parallel without the
need for additional components.
Serial control interface
Serial control of the drivers is provided by an 8-bit shift
register with parallel outputs and an 8-bit latch which
controls the DMOS output stages. Using this configuration
the number of pins needed for control of the eight drivers
is reduced to three; Serial Input (SI), Serial CLock (SCL)
and Serial Input Enable (SIE). When pin SIE is LOW, serial
data at pin SI is shifted into the shift register at each
HIGH-to-LOW transition at the SCL pin and serial data is
shifted out at the Serial Output (SO) pin at a LOW-to-HIGH
transition on the SCL pin. The last bit read in before a
LOW-to-HIGH transition at the SIE pin is bit D8. A HIGH
level at the SI pin causes a driver to switch-on. With a
LOW-to-HIGH transition at the SIE pin, parallel output data
in the shift register is written to the 8-bit latch, which
controls the DMOS outputs. When SIE is HIGH, signals at
pins SI, SCL and SO are disabled. For pin SO this results
in a HIGH level because pin SO is an open-collector
output.
Diagnostic interface
The OLSD detects open loads and short-circuited loads at
each driver stage by comparing its output voltages (Vo) to
a reference voltage (Vref). To allow distinction between
short-circuit and open load conditions, a short-circuit is
detected for Vo > Vref in the on-state, while an open load is
detected for Vo < Vref in the off-state of a driver stage.
In both cases the corresponding status pin is set to a LOW
level and the respective bit in the shift register is inverted
on a HIGH-to-LOW transition of SIE.
By writing a following byte into the shift register, its actual
contents (the control byte eventually modified by errors)
can be read out via pin SO. Comparing this byte with the
original control byte previously written, faults can be
localized and identified (e.g. open load at driver stage
number 5).
Protection of DMOS outputs
Each driver contains a DMOS power FET. The drivers are
protected against overvoltage, short-circuit and
overtemperature conditions.
An overvoltage clamp circuit at each driver causes the
respective DMOS power FET to turn partially on, if its
drain-to-source voltage level exceeds the clamp level
[Vo(clamp)]. Consequently each driver can withstand
voltage peaks caused by turning off inductive loads, such
as relays coils without freewheel diodes. It should be noted
that if outputs are used in parallel the amount of inductive
energy which can be handled will not increase but will
remain equal to that of a single output.
Each driver is protected against a short-circuited load by
current limiting. In the event of a short-circuited load at a
driver stage, the current will be limited and the HIGH level
of its drain-to-source voltage will force the comparator
output to go HIGH. This in turn will set the STATSC pin to
a LOW level.
A two-stage temperature protection circuit is included to
protect the device against overheating caused by high
dissipation in the output transistors.
When the temperature exceeds the overtemperature
threshold level, it will switch-off those outputs with a
short-circuit condition for the duration of the
overtemperature condition. The status and diagnostic
function will not be influenced.
If the chip temperature still rises and exceeds the
emergency threshold level, the emergency shutdown will
become active and shut down all of the outputs until the
temperature drops below the overtemperature threshold.
The outputs are fully protected against short-circuit to
battery conditions for the whole supply voltage range.
To protect the outputs against device threatening
dissipation peaks, the overtemperature control is extended
with local power dissipation sensors. If one or more
outputs dissipate too much power all outputs with a
short-circuit condition will be switched off for the duration
of the local overtemperature condition.
To protect the outputs against high dissipation during load
dump, an overvoltage protection is included. This will
switch-off those outputs with a short-circuit condition if the
supply voltage exceeds the overvoltage threshold VDD(0 V)
for the duration of the overvoltage condition.
The diagnostic and status information will not change due
to the interference of the overvoltage and overtemperature
protections.
To avoid a false LOW signal at the SC pin due to switching
transients at the DMOS outputs, the SC pin is disabled for
a sufficient delay time whenever a new input control byte
has been written into the 8-bit latch with a LOW-to-HIGH
transition of SIE.
1998 Feb 09
5
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| Information | Total 16 Pages | |
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