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부품번호 | TDA9964HL 기능 |
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기능 | 12-bit/ 3.0 V/ 30 Msps analog-to-digital interface for CCD cameras | ||
제조업체 | NXP Semiconductors | ||
로고 | |||
INTEGRATED CIRCUITS
DATA SHEET
TDA9964
12-bit, 3.0 V, 30 Msps
analog-to-digital interface for CCD
cameras
Objective specification
File under Integrated Circuits, IC02
2000 May 02
Philips Semiconductors
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
Objective specification
TDA9964
PINNING
SYMBOL
VCCA1
AGND1
AGND2
IN
AGND3
AGND4
VCCA2
CPCDS1
CPCDS2
DCLPC
OFDOUT
TEST
AGND5
VCCA3
OPGA
OPGAC
SDATA
SCLK
SEN
VSYNC
VCCD1
DGND1
VCCO1
OGND1
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
OGND2
VCCO2
OE
AGND6
2000 May 02
PIN DESCRIPTION
1 analog supply voltage 1
2 analog ground 1
3 analog ground 2
4 input signal from CCD
5 analog ground 3
6 analog ground 4
7 analog supply voltage 2
8 clamp storage capacitor pin 1
9 clamp storage capacitor pin 2
10 regulator decoupling pin
11 analog output of the additional 8-bit control DAC
12 test mode input pin (should be connected to AGND5)
13 analog ground 5
14 analog supply 3
15 PGA output (test pin)
16 PGA complementary output (test pin)
17 serial data input for serial interface control
18 serial clock input for serial interface
19 strobe pin for serial interface
20 vertical sync pulse input
21 digital supply voltage 1
22 digital ground 1
23 output supply voltage 1
24 digital output ground 1
25 ADC digital output 0 (LSB)
26 ADC digital output 1
27 ADC digital output 2
28 ADC digital output 3
29 ADC digital output 4
30 ADC digital output 5
31 ADC digital output 6
32 ADC digital output 7
33 ADC digital output 8
34 ADC digital output 9
35 ADC digital output 10
36 ADC digital output 11 (MSB)
37 output digital ground 2
38 output supply voltage 2
39 output enable control input (LOW: outputs active; HIGH: outputs are high impedance)
40 analog ground 6
4
4페이지 Philips Semiconductors
12-bit, 3.0 V, 30 Msps analog-to-digital
interface for CCD cameras
Objective specification
TDA9964
SYMBOL
PARAMETER
CONDITIONS
MIN.
Digital inputs
PINS: SHP, SHD AND CLK (REFERENCED TO DGND)
VIL LOW-level input voltage
VIH HIGH-level input voltage
Ii input current
0 ≤ Vi ≤ 5.5 V
Zi input impedance
fCLK = 30 MHz
Ci input capacitance
fCLK = 30 MHz
PINS: CLPDM, CLPOB, SEN, SCLK, SDATA, STBY, OE, BLK, VSYNC
VIL LOW-level input voltage
VIH HIGH-level input voltage
Ii input current
0 ≤ Vi ≤ 5.5 V
Clamps
0
2.2
−3
−
−
0
2.2
−2
GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS
tW(clamp)
clamp active pulse width in PGA code = 255 for
number of pixels
maximum 4 LSB error
12
INPUT CLAMP (DRIVEN BY CLPDM)
gm(CDS)
CDS input clamp
transconductance
−
Correlated Double Sampling (CDS)
Vi(CDS)(p-p)
Vreset(max)
Ii(IN)
Ci
tCDS(min)
th(IN;SHP)
th(IN;SHD)
maximum peak-to-peak CDS VCC = 2.85 V
input amplitude (video signal) VCC ≥ 3.0 V
650
800
maximum CDS input reset
pulse amplitude
500
input current into pin IN
at floating gate level
tbf
input capacitance
−
CDS control pulses minimum
active time
CDS input hold time (pin IN)
compared to control pulse
SHP
Vi(CDS)(p-p) = 800 mV
−
black to white transition in
1 pixel with 99% Vi recovery
VCCA = VCCD = 3.0 V;
Tamb = 25 °C;
see Figs 3 and 4
−
CDS input hold time (pin IN)
compared to control pulse
SHD
VCCA = VCCD = 3.0 V;
Tamb = 25 °C;
see Figs 3 and 4
−
Amplifier
DRPGA
∆GPGA
PGA dynamic range
PGA gain step
Analog-to-Digital Converter (ADC)
DNL
differential non linearity
−
0.08
fpix = 30 MHz; ramp input −
TYP.
−
−
−
50
−
−
−
−
−
20
−
−
−
−
2
8
1
1
24
0.10
±0.5
MAX. UNIT
0.6 V
5.5 V
+3 µA
− kΩ
2 pF
0.6 V
5.5 V
+2 µA
− pixels
− mS
− mV
− mV
− mV
tbf µA
− pF
− ns
2 ns
2 ns
− dB
0.12 dB
±0.9 LSB
2000 May 02
7
7페이지 | |||
구 성 | 총 24 페이지수 | ||
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구매 문의 | 일반 IC 문의 : 샘플 및 소량 구매 ----------------------------------------------------------------------- IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한 광범위한 전력 반도체를 판매합니다. 전력 반도체 전문업체 상호 : 아이지 인터내셔날 사이트 방문 : [ 홈페이지 ] [ 블로그 1 ] [ 블로그 2 ] |
부품번호 | 상세설명 및 기능 | 제조사 |
TDA9964HL | 12-bit/ 3.0 V/ 30 Msps analog-to-digital interface for CCD cameras | NXP Semiconductors |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |