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TE28F400CVB80 데이터시트 PDF




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기능 4-MBIT (256K X 16/ 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY
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TE28F400CVB80 데이터시트, 핀배열, 회로
E
PRELIMINARY
4-MBIT (256K X 16, 512K X 8)
SmartVoltage BOOT BLOCK FLASH
MEMORY FAMILY
28F400BV-T/B, 28F400CV-T/B, 28F004BV-T/B
28F400CE-T/B, 28F004BE-T/B
n Intel SmartVoltage Technology
5V or 12V Program/Erase
2.7V, 3.3V or 5V Read Operation
Increased Programming Throughput
at 12V VPP
n Very High-Performance Read
5V: 60/80/120 ns Max. Access Time,
30/40 ns Max. Output Enable Time
3V: 110/150/180 ns Max Access
65/90 ns Max. Output Enable Time
2.7V: 120 ns Max Access 65 ns Max.
Output Enable Time
n Low Power Consumption
Max 60 mA Read Current at 5V
Max 30 mA Read Current at
2.7V–3.6V
n x8/x16-Selectable Input/Output Bus
28F400 for High Performance 16- or
32-bit CPUs
n x8-Only Input/Output Architecture
28F004B for Space-Constrained
8-bit Applications
n Optimized Array Blocking Architecture
One 16-KB Protected Boot Block
Two 8-KB Parameter Blocks
One 96-KB Main Block
Three 128-KB Main Blocks
Top or Bottom Boot Locations
n Absolute Hardware-Protection for Boot
Block
n Software EEPROM Emulation with
Parameter Blocks
n Extended Temperature Operation
–40°C to +85°C
n Extended Cycling Capability
100,000 Block Erase Cycles
(Commercial Temperature)
10,000 Block Erase Cycles
(Extended Temperature)
n Automated Word/Byte Program and
Block Erase
Industry-Standard Command User
Interface
Status Registers
Erase Suspend Capability
n SRAM-Compatible Write Interface
n Automatic Power Savings Feature
1 mA Typical ICC Active Current in
Static Operation
n Reset/Deep Power-Down Input
0.2 µA ICCTypical
Provides Reset for Boot Operations
n Hardware Data Protection Feature
Write Lockout during Power
Transitions
n Industry-Standard Surface Mount
Packaging
40-Lead TSOP
44-Lead PSOP: JEDEC ROM
Compatible
48-Lead TSOP
56-Lead TSOP
n Footprint Upgradeable from 2-Mbit and
to 8-Mbit Boot Block Flash Memories
n ETOX™ IV Flash Technology
July 1997
Order Number: 290530-005




TE28F400CVB80 pdf, 반도체, 판매, 대치품
4-MBIT SmartVoltage BOOT BLOCK FAMILY
E
Number
-001
-002
-003
-004
-005
REVISION HISTORY
Description
Initial release of datasheet.
Status changed from Product Preview to Preliminary
28F400CV/CE/BE references and information added throughout.
2.7V CE/BE specs added throughout.
The following sections have been changed or rewritten: 1.1, 3.0, 3.2.1, 3.2.2, 3.3.1,
3.3.1.1, 3.3.2, 3.3.2.1, 3.3.3, 3.3.4, 3.6.2.
Note 2 added to Figure 3 to clarify 28F008B pinout vs. 28F008SA.
Sentence about program and erase WSM timeout deleted from Section 3.3.3, 3.3.4.
Erroneous arrows leading out of error states deleted from flowcharts in Figs. 9, 10.
Sections 5.1, 6.1 changed to “Applying VCC Voltages.” These sections completely
changed to clarify VCC ramp requirements.
IPPD 3.3V Commercial spec changed from 10 to 5 µA.
Capacitance tables added after commercial and extended DC Characteristics tables.
Test and slew rate notes added to Figs. 12, 13, 19, 20, 21.
Test configuration drawings (Fig. 14, 22) consolidated into one, with component
values in table. (Component values also rounded off).
tELFL, tELFH, tAVFL changed from 7 to 5 ns for 3.3V BV-60 commercial and 3.3V
TBV-80 extended, 10 to 5 ns for 3.3V BV-80 and BV-120 commercial.
tWHAX and tEHAX changed from 10 to 0 ns.
tPHWL changed from 1000 ns to 800 ns for 3.3V BV-80, BV-120 commercial.
tPHEL changed from 1000 ns to 800 ns for 3.3V BV-60, BV-80, and BV-120 commercial.
28F400BE row removed from Table 1
Applying VCC voltages (Sections 5.1 and 6.1) rewritten for clarity.
Minor cosmetic changes/edits.
Corrections: Spec typographical error “tQWL” corrected to read “tQVVL.”
Intel386™ EX Microprocessor block diagram updated because latest Intel386 CPU
specs require less glue logic.
Spec tELFL and tELFH changed from 5 ns (max) to 0 ns (min).
New specs tPLPH and tPLQX added from Specification Update document (297595).
Specs tEHQZ and tGHQZ improved on most voltage/speed combinations.
Correction: Appendix A, Ordering information fixed order numbers from TE27F400BVT80
to TE28F400BVT80 and TE27F400BVB80 to TE28F400BVB80.
Updated disclaimer.
4 PRELIMINARY

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TE28F400CVB80 전자부품, 판매, 대치품
E
4-MBIT SmartVoltage BOOT BLOCK FAMILY
1.3 Applications
The 4-Mbit boot block flash memory family
combines high-density, low-power, high-
performance, cost-effective flash memories with
blocking and hardware protection capabilities. Their
flexibility and versatility reduce costs throughout the
product life cycle. Flash memory is ideal for Just-In-
Time production flow, reducing system inventory
and costs, and eliminating component handling
during the production phase.
When your product is in the end-user’s hands, and
updates or feature enhancements become
necessary, flash memory reduces the update costs
by allowing user-performed code changes instead
of costly product returns or technician calls.
The 4-Mbit boot block flash memory family provides
full-function, blocked flash memories suitable for a
wide range of applications. These applications
include extended PC BIOS and ROM-able
applications storage, digital cellular phone program
and data storage, telecommunication boot/firmware,
printer firmware/font storage and various other
embedded applications where program and data
storage are required.
Reprogrammable systems, such as personal
computers, are ideal applications for the 4-Mbit
flash memory products. Increasing software
sophistication greatens the probability that a code
update will be required after the PC is shipped. For
example, the emerging of “plug and play” standard
in desktop and portable PCs enables auto-
configuration of ISA and PCI add-in cards.
However, since the “plug and play” specification
continues to evolve, a flash BIOS provides a cost-
effective capability to update existing PCs. In
addition, the parameter blocks are ideal for storing
the required auto-configuration parameters,
allowing you to integrate the BIOS PROM and
parameter storage EEPROM into a single
component, reducing parts costs while increasing
functionality.
The 4-Mbit flash memory products are also
excellent design solutions for digital cellular phone
and telecommunication switching applications
requiring very low power consumption, high-
performance, high-density storage capability,
modular software designs, and a small form factor
package. The 4-Mbit’s blocking scheme allows for
easy segmentation of the embedded code with
16 Kbytes of hardware-protected boot code, four
main blocks of program code and two parameter
blocks of 8 Kbytes each for frequently updated data
storage and diagnostic messages (e.g., phone
numbers, authorization codes).
Intel’s boot block architecture provides a flexible
voltage solution for the different design needs of
various applications. The asymmetrically-blocked
memory map allows the integration of several
memory components into a single flash device. The
boot block provides a secure boot PROM; the
parameter blocks can emulate EEPROM
functionality for parameter store with proper
software techniques; and the main blocks provide
code and data storage with access times fast
enough to execute code in place, decreasing RAM
requirements.
1.4 Pinouts
Intel’s SmartVoltage Boot Block architecture
provides upgrade paths in every package pinout to
the 8-Mbit density. The 28F004B 40-lead TSOP
pinout for space-constrained designs is shown in
Figure 3. The 28F400 44-lead PSOP pinout follows
the industry-standard ROM/EPROM pinout, as
shown in Figure 4. For designs that require x16
operation but have space concerns, refer to the
48-lead pinout in Figure 5. Furthermore, the 28F400
56-lead TSOP pinout shown in Figure 6 provides
density upgrades to future higher density boot block
memories.
Pinouts for the corresponding 2-Mbit and 8-Mbit
components are also provided for convenient
reference. 4-Mbit pinouts are given on the chip
illustration in the center, with 2-Mbit and 8-Mbit
pinouts going outward from the center.
PRELIMINARY
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TE28F400CVB80

4-MBIT (256K X 16/ 512K X 8)SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY

Intel Corporation
Intel Corporation

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