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PDF TEA5170 Data sheet ( Hoja de datos )
| Número de pieza | TEA5170 | |
| Descripción | SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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TEA5170
SWITCH MODE POWER SUPPLY SECONDARY CIRCUIT
........... INTERNAL PWM SIGNAL GENERATOR
POWER SUPPLY WIDE RANGE 4.5V – 14.5V
SOFT START
REFERENCE VOLTAGE 2V ± 5%
WIDE FREQUENCY RANGE 250kHz
MINIMUM OUTPUT PULSE WIDTH 500nS
MAXIMUM PRESET DUTY CYCLE
SYNCHRONIZATION WINDOW
OUTPUT SWITCH
UNDERVOLTAGE LOCKOUT
FREQUENCY RANGE WITH SYNCHRONIZA-
TION 64kHz
DESCRIPTION
The TEA5170 is designed to work in the secondary
part of an off-line SMPS, sending pulses to the
slaved TEA2260/61 which are located on the pri-
mary side of the main transformer. An accurate
regulated voltage is obtained by duty cycle control.
The TEA5170 can be externally synchronized by
higher or lower frequency signal, then it could be
used in applications like TV set ones. For more
details, refer to application note AN408/0591.
PIN CONNECTIONS
DIP8
(Plastic Package)
ORDER CODE : TEA5170
SOFT-START CAPACITOR CSF
SUPPLY VOLTAGE VCC
POWER OUTPUT POUT
GROUND GND
1
2
3
4
8 RT OSCILLATOR RESISTOR
7 CT OSCILLATOR CAPACITOR
6 E OUT VOLTAGE ERROR AMPLIFIER OUTPUT
5
E
VOLTAGE ERROR AMPLIFIER
INVERTING INPUT
September 1993
1/9
1 page  
Figure 3
UNSYNCHRONIZED
MODE
Vct
Vtsy
SYNCHRONIZED MODE
TEA5170
UNSYNCHRONIZED
MODE
Vrt
Wtrig- Wtrig+
Remark : In case of an application between
TEA5170 and TEA2164, to optimize the
synchronization windows of these
circuits, the following relations have to
be
used
:
Tm
=
T1S.Y0N6CTe
=
Tm
1.223
with Te : Free period of the TEA2164
oscillator, and Tm : Free period of the
TEA5170 oscillator.
BLOCK DESCRIPTION
The error voltage amplifier inverting-input and out-
put are accessible to use different feed-back net-
work and allowing parasitic filtering network. The
non-inverting input is internaly connected to 2V
reference voltage.
The RC oscillator is designed to work at high
frequency (up to 250kHz). RT sets the capacitor
charging current Io = 2/RT.
The capacitor CT is loaded from V1 ≈ 1V to V2 = 2V
during
T1
=
CT RT
1.985
and
then
down
loaded
through
an integrated resistor R2 ≈ 1kΩ during T2 = 1300 CT
The ramp is used to limit the duty cycle. Then the
maximum duty cycle is
DONMAX
=
T1
1
+
T2
(0.73
T1
+
T2)
The output level is VCC independant when VCC is
over 8V.
The VCC monitoring switches the circuit on when
VCC is over 4V and switches it off when under 3.8V.
This function insures a proper starting procedure
(made by the primary side circuit).
SYNCHRONIZATION
(see Figures 4 and 5)
Figure 4 : Triggering Schematic
VCC
7
Ct 1kΩ
from logic
Network
8
Rt
2.7V
2.7V
+
- towards logic
Figure 5 : Typical Waveforms
Vct
Vrt 2.7V
2V
TtrigP
1V
5/9
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet TEA5170.PDF ] | |
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