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TH58100FT 데이터시트 PDF




Toshiba Semiconductor에서 제조한 전자 부품 TH58100FT은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 TH58100FT 기능
기능 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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TH58100FT 데이터시트, 핀배열, 회로
TH58100FT
TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
1-GBIT (128M ´ 8 BITS) CMOS NAND E2PROM
DESCRIPTION
The TH58100 is a single 3.3 V 1-Gbit (1,107,296,256) bit NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E2PROM) organized as 528 bytes ´ 32 pages ´ 8192 blocks. The device has a 528-byte
static register which allows program and read data to be transferred between the register and the memory cell array
in 528-byte increments. The Erase operation is implemented in a single block unit (16 Kbytes + 512 bytes: 528 bytes
´ 32 pages).
The TH58100 is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and Program operations are automatically executed making the device most
suitable for applications such as solid-state file storage, voice recording, image file memory for still cameras and
other systems which require high-density non-volatile memory data storage.
FEATURES
· Organization
Memory cell allay 528 ´ 128K ´ 8 ´ 2
Register
528 ´ 8
Page size
528 bytes
Block size
(16K + 512) bytes
· Modes
Read, Reset, Auto Page Program
Auto Block Erase, Status Read
Multi Block Program, Multi Block Erase
· Mode control
Serial input/output
Command control
· Power supply
VCC = 2.7 V to 3.6 V
· Program/Erase Cycles 1E5 cycle (with ECC)
· Access time
Cell array to register 25 ms max
Serial Read Cycle 50 ns min
· Operating current
Read (50 ns cycle) 10 mA typ.
Program (avg.)
10 mA typ.
Erase (avg.)
10 mA typ.
Standby
100 mA
· Package
TSOPI48-P-1220-0.50 (Weight: 0.53 g typ.)
PIN ASSIGNMENT (TOP VIEW)
PIN NAMES
NC
NC
NC
NC
NC
GND
RY / BY
RE
CE
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 NC
47 NC
46 NC
45 NC
44 I/O8
43 I/O7
42 I/O6
41 I/O5
40 NC
39 NC
38 NC
37 VCC
36 VSS
35 NC
34 NC
33 NC
32 I/O4
31 I/O3
30 I/O2
29 I/O1
28 NC
27 NC
26 NC
25 NC
I/O1 to I/O8
CE
WE
RE
CLE
ALE
WP
RY/BY
GND
VCC
VSS
I/O port
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Write protect
Ready/Busy
Ground input
Power supply
Ground
000707EBA1
· TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide
for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
· The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control
instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document
shall be made at the customer’s own risk.
· The products described in this document are subject to the foreign exchange and foreign trade laws.
· The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or
others.
· The information contained herein is subject to change without notice.
2001-03-05 1/43




TH58100FT pdf, 반도체, 판매, 대치품
TH58100FT
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0° to 70°C, VCC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
tCLS
tCLH
tCS
tCH
tWP
tALS
tALH
tDS
tDH
tWC
tWH
tWW
tRR
tRP
tRC
tREA
tCEH
tREAID
tOH
tRHZ
tCHZ
tREH
tIR
tRSTO
tCSTO
tRHW
tWHC
tWHR
tAR1
tCR
tR
tWB
tAR2
tRB
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time (Serial Data Access)
CE High Time for Last Address in Serial Read Cycle
RE Access Time (ID Read)
Data Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
Output-High-impedance-to- RE Rising Edge
RE Access Time (Status Read)
CE Access Time (Status Read)
RE High to WE Low
WE High to CE Low
WE High to RE Low
ALE Low to RE Low (ID Read)
CE Low to RE Low (ID Read)
Memory Cell Array to Starting Address
WE High to Busy
ALE Low to RE Low (Read Cycle)
RE Last Clock Rising Edge to Busy (in Sequential Read)
tCRY CE High to Ready (When interrupted by CE in Read Mode)
tRST Device Reset Time (Read/Program/Erase)
MIN
MAX
UNIT
0¾
10 ¾
0¾
10 ¾
25 ¾
0¾
10 ¾
20 ¾
10 ¾
50 ¾
15 ¾
100 ¾
20 ¾
35 ¾
50 ¾
¾ 35
100 ¾
¾ 35
10 ¾
¾ 30
¾ 20
15 ¾
0¾
¾ 35
¾ 45
0¾
30 ¾
30 ¾
100 ¾
100 ¾
¾ 25
¾ 200
50 ¾
¾ 200
1+
¾
tr ( RY/BY )
¾ 6/10/500
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
ms
ms
NOTES
(2)
(1) (2)
AC TEST CONDITIONS
PARAMETER
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
CONDITION
2.4 V, 0.4 V
3 ns
1.5 V, 1.5 V
1.5 V, 1.5 V
CL (100 pF) + 1 TTL
2001-03-05 4/43

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TH58100FT 전자부품, 판매, 대치품
Address Input Cycle Timing Diagram
TH58100FT
CLE
CE
WE
ALE
I/O1
to I/O8
tCLS
tCS tWC tWC tWC
tWP tWH tWP tWH tWP tWH tWP
tALS
tALH
tDS tDH
A0 to A7
tDS tDH
A9 to A16
tDS tDH
A17 to A24
tDS tDH
A25 to A26
: VIH or VIL
Data Input Cycle Timing Diagram
CLE
CE
ALE
WE
I/O1
to I/O8
tALS
tWC
tWP tWH tWP
tDS tDH
DIN0
tDS tDH
DIN1
tCLH
tCH
tWP
tDS tDH
DIN527
: VIH or VIL
2001-03-05 7/43

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