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P83C748EBDDB 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
83C748/87C748
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
Supersedes data of 1998 Apr 23
IC20 Data Handbook
1999 Apr 15
Philips
Semiconductors




P83C748EBDDB pdf, 반도체, 판매, 대치품
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
83C748/87C748
PIN DESCRIPTIONS
MNEMONIC
VSS
VCC
P0.0–P0.2
PIN NO.
DIP/
SSOP
LCC
12 14
24 28
8–6 9–7
67
78
89
TYPE
NAME AND FUNCTION
I Circuit Ground Potential
I Supply voltage during normal, idle, and power-down operation.
I/O Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance inputs. These pins are driven low if the port register
bit is written with a 0. The state of the pin can always be read from the port register by the program.
P0.0 and P0.1 are open drain bidirectional I/O pins. While these differ from “standard TTL”
characteristics, they are close enough for the pins to still be used as general-purpose I/O. Port 0
also provides alternate functions for programming the EPROM memory as follows:
N/A VPP (P0.2) – Programming voltage input. (See Note 1).
I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
P1.0–P1.7
13–20 15–20, I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
23, 24
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical
Characteristics: IIL). Port 1 serves to output the addressed EPROM contents in the verify mode and
accepts as inputs the value to program into the selected address during the program mode. Port 1
also serves the special function features of the 80C51 family as listed below:
18 20 I INT0 (P1.5): External interrupt.
19 23 I INT1 (P1.6): External interrupt.
20 24 I T0 (P1.7): Timer 0 external input.
P3.0–P3.7
5–1, 6, 4–1, I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
23–21 27–25
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to be
programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL.
RST
X1
9 11 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to
VCC. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
the device in the programming state allowing programming address, data and VPP to be applied for
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
11 13 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2 10 12 O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
1. When P0.2 is at or close to 0 volts, it may affect the internal ROM operation. It is recommended that P0.2 be tied to VCC via a small pull-up
(e.g. 2kW).
ABSOLUTE MAXIMUM RATINGS1, 2
PARAMETER
RATING
UNIT
Storage temperature range
–65 to +150
°C
Voltage from VCC to VSS
Voltage from any pin to VSS (except VPP)
Power dissipation
–0.5 to +6.5
–0.5 to VCC + 0.5
1.0
V
V
W
Voltage on VPP pin to VSS
0 to +13.0
V
Maximum IOL per I/O pin
10 mA
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
1999 Apr 15
4

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P83C748EBDDB 전자부품, 판매, 대치품
Philips Semiconductors
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
83C748/87C748
22
20
18
16
ICC (mA)
14
12
10
8
6
4
2
MAX ACTIVE ICC5
TYP ACTIVE ICC5
MAX IDLE ICC6
TYP IDLE ICC6
4MHz
8MHz 12MHz 16MHz
FREQ
SU00298
Figure 2. ICC vs. FREQ
Maximum ICC values taken at VCC max and worst case temperature.
Typical ICC values taken at VCC = 5.0V and 25°C.
Notes 5 and 6 refer to DC Electrical Characteristics.
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-up, the voltage on
VCC and RST must come up at the same time for a proper start-up.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. the control
bits for the reduced power modes are in the special function register
PCON.
Table 1. External Pin Status During Idle and
Power-Down Modes
MODE
Port 0
Port 1
Port 2
Idle
Power-down
Data
Data
Data
Data
Data
Data
1999 Apr 15
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P83C748EBDDB

80C51 8-bit microcontroller family 2K/64 OTP/ROM/ low pin count

NXP Semiconductors
NXP Semiconductors
P83C748EBDDB

80C51 8-bit microcontroller family 2K/64 OTP/ROM/ low pin count

NXP Semiconductors
NXP Semiconductors

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