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기능 80C51 8-bit microcontroller family 1K/64 OTP ROM/ low pin count
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P87C750 데이터시트, 핀배열, 회로
INTEGRATED CIRCUITS
83C750/87C750
80C51 8-bit microcontroller family
1K/64 OTP ROM, low pin count
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Philips
Semiconductors




P87C750 pdf, 반도체, 판매, 대치품
Philips Semiconductors
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
Product specification
83C750/87C750
PIN DESCRIPTIONS
PIN NO.
MNEMONIC DIP/ LCC TYPE
SSOP
NAME AND FUNCTION
VSS
VCC
P0.0-P0.2
12 14
I Circuit Ground Potential
24 28
I Supply voltage during normal, idle, and power-down operation.
8-6 9-7 I/O Port 0: Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance inputs. These pins are driven low if the port register
bit is written with a 0. The state of the pin can always be read from the port register by the program.
P0.0, P0.1, and P0.2 are open drain bidirectional I/O pins with the electrical characteristics listed in
the tables that follow. While these differ from “standard TTL” characteristics, they are close enough
for the pins to still be used as general-purpose I/O. Port 0 also provides alternate functions for
programming the EPROM memory as follows:
6 7 N/A VPP (P0.2) – Programming voltage input. (See Note 1.)
7 8 I OE/PGM (P0.1) – Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
8 9 I ASEL (P0.0) – Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
P1.0-P1.7
13-20 15-20, I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
23, 24
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: IIL). Port 1 serves to output the addressed EPROM contents in the verify
mode and accepts as inputs the value to program into the selected address during the program
mode. Port 1 also serves the special function features of the 80C51 family as listed below:
18 20
I INT0 (P1.5): External interrupt.
19 23
I INT1 (P1.6): External interrupt.
20 24
I T0 (P1.7): Timer 0 external input.
P3.0-P3.7
5-1, 6, 4-1, I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
23-21 27-25
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: IIL). Port 3 also functions as the address input for the EPROM memory location to
be programmed (or verified). The 10-bit address is multiplexed into this port as specified by
P0.0/ASEL.
RST
9 11 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to VSS permits a power-on RESET using only an external capacitor to
VCC. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
the device in the programming state allowing programming address, data and VPP to be applied for
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
X1 11 13 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
X2 10 12 O Crystal 2: Output from the inverting oscillator amplifier.
NOTE:
1. When P0.2 is at or close to 0 Volt, it may affect the internal ROM operation. We recommend that P0.2 be tied to VCC via a small pull-up (e.g.,
2k).
OSCILLATOR CHARACTERISTICS
X1 and X2 are the input and output, respectively, of an inverting
amplifier which can be configured for use as an on-chip oscillator.
To drive the device from an external clock source, X1 should be
driven while X2 is left unconnected. There are no requirements on
the duty cycle of the external clock signal, because the input to the
internal clock circuitry is through a divide-by-two flip-flop. However,
minimum and maximum high and low times specified in the data
sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-up reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-up, the voltage on
VCC and RST must come up at the same time for a proper start-up.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset.
1998 May 01
4

4페이지










P87C750 전자부품, 판매, 대치품
Philips Semiconductors
80C51 8-bit microcontroller family
1K/64 OTP/ROM, low pin count
Product specification
83C750/87C750
DC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1
TEST
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNIT
VIL
VIH
VIH1
VOL
VOL1
Input low voltage
Input high voltage, except X1, RST
Input high voltage, X1, RST
Output low voltage, ports 1 and 3
Output low voltage, port 0
IOL = 1.6mA2
IOL = 3.2mA2
–0.5
0.2VCC+0.9
0.7VCC
0.2VDD–0.1
VCC+0.5
VCC+0.5
0.45
0.45
V
V
V
V
V
VOH Output high voltage, ports 1 and 3
IOH = –60µA
IOH = –25µA
IOH = –10µA
2.4
0.75VCC
0.9VCC
V
V
V
C Capacitance
10 pF
IIL Logical 0 input current, ports 1 and 3
VIN = 0.45V
ITL Logical 1 to 0 transition current, ports 1 and 33
VIN = 2V (0 to +70°C)
VIN = 2V (–40 to +85°C)
ILI Input leakage current, port 0
0.45 < VIN < VCC
–50
–650
–750
±10
µA
µA
µA
µA
RRST
Internal pull-down resistor
25 175 k
CIO Pin capacitance
IPD Power-down current4
Test freq = 1MHz,
Tamb = 25°C
VCC = 2 to VCC max
10 pF
50 µA
VPP VPP program voltage
VSS = 0V
VCC = 5V±10%
Tamb = 21°C to 27°C
12.5
13.0
V
IPP Program current
VPP = 13.0V
50 mA
ICC Supply current (see Figure 3)5, 6
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
2. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin:
10mA
(NOTE: This is 85°C spec.)
Maximum IOL per 8-bit port:
26mA
Maximum total IOL for all outputs:
67mA
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
4. Power-down ICC is measured with all output pins disconnected; port 0 = VCC; X2, X1 n.c.; RST = VSS.
5. Active ICC is measured with all output pins disconnected; X1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;
RST = port 0 = VCC. ICC will be slightly higher if a crystal oscillator is used.
6. Idle ICC is measured with all output pins disconnected; X1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC – 0.5V; X2 n.c.;
port 0 = VCC; RST = VSS.
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C or –40°C to +85°C, VCC = 5V ±10%, VSS = 0V1, 2
VARIABLE CLOCK
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/tCLCL
Oscillator frequency:
External Clock (Figure 2)
3.5 16 3.5 40 MHz
tCHCX
High time
20 10 ns
tCLCX
Low time
20 10 ns
tCLCH
Rise time
20 20 ns
tCHCL
Fall time
20 20 ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
2. Load capacitance for ports = 80pF.
1998 May 01
7

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