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부품번호 SMP04ES 기능
기능 CMOS Quad Sample-and-Hold Amplifier
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SMP04ES 데이터시트, 핀배열, 회로
a
FEATURES
Four Independent Sample-and-Holds
Internal Hold Capacitors
High Accuracy: 12 Bit
Very Low Droop Rate: 2 mV/s typ
Output Buffers Stable for CL 500 pF
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Applications
Monolithic Low Power CMOS Design
APPLICATIONS
Signal Processing Systems
Multichannel Data Acquisition Systems
Automatic Test Equipment
Medical and Analytical Instrumentation
Event Analysis
DAC Deglitching
CMOS Quad
Sample-and-Hold Amplifier
SMP04*
FUNCTIONAL BLOCK DIAGRAM
VDD
SMP04
VIN1
S/H1
VIN2
S/H2
VIN3
S/H3
VIN4
S/H4
VSS
VSS
VSS
VSS
VOUT1
VOUT2
VOUT3
VOUT4
DGND
VSS
GENERAL DESCRIPTION
The SMP04 is a monolithic quad sample-and-hold; it has four
internal precision buffer amplifiers and internal hold capacitors.
It is manufactured in ADI’s advanced oxide isolated CMOS
technology to obtain the high accuracy, low droop rate and fast
acquisition time required by data acquisition and signal process-
ing systems. The device can acquire an 8-bit input signal to
± 1/2 LSB in less than four microseconds. The SMP04 can
operate from single or dual power supplies with TTL/CMOS
logic compatibility. Its output swing includes the negative supply.
The SMP04 is ideally suited for a wide variety of sample-and-
hold applications, including amplifier offset or VCA gain adjust-
ments. One or more can be used with single or multiple DACs
to provide multiple setpoints within a system.
The SMP04 offers significant cost and size reduction over
equivalent module or discrete designs. It is available in a
16-lead hermetic or plastic DIP and surface mount SOIC
packages. It is specified over the extended industrial tem-
perature range of –40°C to +85°C.
*Protected by U.S. Patent No. 4,739,281.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998




SMP04ES pdf, 반도체, 판매, 대치품
SMP04
VOUT1
VOUT2 VDD VOUT3
VOUT4
VIN1
VIN2
VSS
VIN4
S/H1
VIN3
S/H2 DGND
S/H3 S/H4
Dice Characteristics
Die Size: 0.80 x 0.120 mil = 9,600 sq. mil
(2.032 x 3.048mm = 6.193 sq. mm)
WAFER TEST LIMITS (@ VDD = +12 V, VSS = DGND = 0 V, RL = No Load, TA = +25؇C, unless otherwise noted.)
Parameter
Symbol
Conditions
SMP04G
Limits
Units
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current
Output Sink Current
Output Voltage Range
VOS
VHS
V/t
ISOURCE
ISINK
OVR
VIN = +6 V
VIN = +6 V
VIN = +6 V
VIN = +6 V
VIN = +6 V
RL = 20 k
RL = 10 k
± 10
±4
25
1.2
0.5
0.06/10.0
0.06/9.5
mV max
mV max
mV/s max
mA min
mA min
V min/max
V min/max
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
VINH
VINL
IIN
2.4 V min
0.8 V max
1 µA max
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Power Dissipation
PSRR
IDD
PDIS
10.8 V VDD 13.2 V
60
7
84
dB min
mA max
mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
–4– REV. D

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SMP04ES 전자부품, 판매, 대치품
SMP04
GENERAL INFORMATION
The SMP04 is a quad sample-and-hold with each track-and-
hold having its own input, output, control, and on-chip hold
capacitor. The combination of four high performance track-and-
hold capacitors on a single chip greatly reduces board space and
design time while increasing reliability.
After the device selection, the primary considerations in using
track-and-holds are the hold capacitor and layout. The SMP04
eliminates most of these problems by having the hold capacitors
internal, eliminating the problems of leakage, feedthrough,
guard ring layout and dielectric absorption.
POWER SUPPLIES
The SMP04 is capable of operating with either single or dual
supplies over a voltage range of 7 to 15 volts. Based on the
supply voltages chosen, VDD and VSS establish the output volt-
age range, which is:
VSS + 0.05 V VOUT VDD –2 V
Note that several specifications, including acquisition time,
offset and output voltage compliance will degrade for a total
supply voltage of less than 7 V. Positive supply current is typi-
cally 4 mA with the outputs unloaded. The SMP04 has an inter-
nally regulated TTL supply so that TTL/CMOS compatibility
will be maintained over the full supply range.
Single Supply Operation Grounding Considerations
In single supply applications, it is extremely important that the
VSS (negative supply) pin be connected to a clean ground. This
is because the hold capacitor is internally tied to VSS. Any noise
or disturbance in the ground will directly couple to the output of
the sample-and-hold, degrading the signal-to-noise performance.
It is advisable that the analog and digital ground traces on the
circuit board be physically separated to reduce digital switching
noise from entering the analog circuitry.
Power Supply Bypassing
For optimum performance, the VDD supply pin must also be
bypassed with a good quality, high frequency ceramic capacitor.
The recommended value is 0.1 µF. In the case where dual sup-
plies are used, VSS (negative supply) bypassing is particularly
important. Again this is because the internal hold capacitor is
tied to VSS. Good bypassing prevents high frequency noise from
entering the sample-and-hold amplifier. A 0.1 µF ceramic bypass
capacitor is generally sufficient. For high noise environments,
adding a 10 µF tantalum capacitor in parallel with the 0.1 µF
provides additional protection.
Power Supply Sequencing
It may be advisable to have the VDD turn on prior to having logic
levels on the inputs. The SMP04 has been designed to be resis-
tant to latch-up, but standard precautions should still be taken.
OUTPUT BUFFERS (Pins 1, 2, 14 and 15)
The buffer offset specification is ±10 mV; this is less than 1/2 LSB
of an 8-bit DAC with 10 V full scale. Change in offset over the
output range is typically 3 mV. The hold step is the magnitude
of the voltage step caused when switching from sample-to-hold
mode. This error is sometimes referred to as the pedestal
error or sample-to-hold offset, and is about 2 mV with little
variation. The droop rate of a held channel is 2 µV/ms typical
and ± 25 µV/ ms maximum.
The buffers are designed primarily to drive loads connected to
ground. The outputs can source more than 1.2 mA each, over
the full voltage range and maintain specified accuracy. In split
supply operation, symmetrical output swings can be obtained by
restricting the output range to 2 V from either supply.
On-chip SMP04 buffers eliminate potential stability problems
associated with external buffers; outputs are stable with capaci-
tive loads up to 500 pF. However, since the SMP04’s buffer
outputs are not short-circuit protected, care should be taken to
avoid shorting any output to the supplies or ground.
SIGNAL INPUT (Pins 3, 5, 11 and 12)
The signal inputs should be driven from a low impedance
voltage source such as the output of an op amp. The op amp
should have a high slew rate and fast settling time if the SMP04’s
fast acquisition time characteristics are to be maintained. As
with all CMOS devices, all input voltages should be kept within
range of the supply rails (VSS VIN VDD) to avoid the possibil-
ity of setting up a latch-up condition.
The internal hold capacitance is typically 60 pF and the internal
switch ON resistance is 2 k.
If single supply operation is desired, op amps such as the OP183
or AD820, that have input and output voltage compliances
including ground, can be used to drive the inputs. Split sup-
plies, such as ± 7.5 V, can be used with the SMP04 and the
above mentioned op amps.
APPLICATION TIPS
All unused digital inputs should be connected to logic LOW
and the analog inputs connected to analog ground. For connec-
tors or driven analog inputs that may become temporarily dis-
connected, a resistor to VSS or analog ground should be used
with a value ranging from 0.2 Mto 1 M.
Do not apply signals to the SMP04 with power off unless the
input current’s value is limited to less than 10 mA.
Track-and-holds are sensitive to layout and physical connections.
For the best performance, the SMP04 should not be socketed.
REV. D
–7–

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