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PDF SMP18FP Data sheet ( Hoja de datos )
| Número de pieza | SMP18FP | |
| Descripción | Octal Sample-and-Hold with Multiplexed Input | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Octal Sample-and-Hold
with Multiplexed Input
SMP18
FEATURES
High Speed Version of SMP08
Internal Hold Capacitors
Low Droop Rate
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Operation
Break-Before-Make Channel Addressing
Compatible With CD4051 Pinout
Low Cost
APPLICATIONS
Multiple Path Timing Deskew for A.T.E.
Memory Programmers
Mass Flow/Process Control Systems
Multichannel Data Acquisition Systems
Robotics and Control Systems
Medical and Analytical Instrumentation
Event Analysis
Stage Lighting Control
GENERAL DESCRIPTION
The SMP18 is a monolithic octal sample-and-hold; it has eight
internal buffer amplifiers, input multiplexer, and internal hold
capacitors. It is manufactured in an advanced oxide isolated
CMOS technology to obtain high accuracy, low droop rate, and
fast acquisition time. The SMP18 has a typical linearity error of
only 0.01% and can accurately acquire a 10-bit input signal to
± 1/2 LSB in less than 2.5 microseconds. The SMP18’s output
swing includes the negative supply in both single and dual sup-
ply operation.
The SMP18 was specifically designed for systems that use a
calibration cycle to adjust a multiple of system parameters. The
low cost and high level of integration make the SMP18 ideal for
calibration requirements that have previously required an ASIC,
or high cost multiple D/A converters.
The SMP18 is also ideally suited for a wide variety of sample-
and-hold applications including amplifier offset or VCA gain ad-
justments. One or more SMP18s can be used with single or
multiple DACs to provide multiple set points within a system.
FUNCTIONAL BLOCK DIAGRAM
(LSB)
INPUT A
(MSB)
B C INH
3 11 10 9
6
1 OF 8 DECODER
SW
SW
SW
SW
SW
SW
SW
SW
HOLD CAPS
(INTERNAL)
SMP18
8 DGND
16 VDD
13 CH0OUT
14 CH1OUT
15 CH2OUT
12 CH3OUT
1 CH4OUT
5 CH5OUT
2 CH6OUT
4 CH7OUT
7 VSS
The SMP18 offers significant cost and size reduction over
discrete designs. It is available in a 16-pin plastic DIP, a
narrow body SO-16 surface-mount SOIC package or the thin
TSSOP-16 package. The SMP18 is a higher speed direct
replacement for the SMP08.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
1 page  
0
VDD = +12V
–1 VSS = 0V
–2 VIN = +5V
RL = 10kΩ
–3
–4
–5
–6
–7
–8
–55 –35 –15 5 25 45 65 85 105 125
TEMPERATURE – °C
Offset Voltage vs. Temperature
Typical Performance Characteristics–SMP18
14
VSS = 0V
NO LOAD
12
10
8
6
+85°C
+25°C
4 –40°C
2
4 6 8 10 12 14 16 18
VDD – Volts
Supply Current vs. VDD
90
80
70
60
50
40
30
20
10
0
10
–PSRR
+PSRR
VDD = +12V
VSS = 0V
VIN = +6V
TA = +25°C
NO LOAD
100 1k
10k 100k
FREQUENCY – Hz
1M
Sample Mode Power Supply Rejection
2
1
0
–1
–2
–3
–4
–5
100
VDD = +6V
VSS = –6V
TA = +25°C
NO LOAD
90
45
0
–45
PHASE
–90
GAIN
–135
–180
1k 10k 100k 1M
FREQUENCY – Hz
–225
10M
Gain, Phase Shift vs. Frequency
15
VDD = +6V
VSS = –6V
12 TA = +25°C
NO LOAD
9
6
3
0
10k 100k
1M
FREQUENCY – Hz
10M
Maximum Output Voltage vs.
Frequency
35
VDD = +12V
30 VSS = 0V
TA = +25°C
25 NO LOAD
20
15
10
5
0
10 100
1k 10k 100k
FREQUENCY – Hz
1M
Output Impedance vs. Frequency
60
50
+PSRR
40
VDD = +12V
30 VSS = 0V
TA = +25°C
20 NO LOAD
10 HOLD CAPACITORS
REFERENCED TO VSS
0
–PSRR
–10
10
100 1k
10k 100k
FREQUENCY – Hz
1M
Hold Mode Power Supply Rejection
REV. C
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SMP18FP.PDF ] | |
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