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PDF SLX24C04P Data sheet ( Hoja de datos )
| Número de pieza | SLX24C04P | |
| Descripción | 4 Kbit 512 x 8 bit Serial CMOS EEPROMs/ I2C Synchronous 2-Wire Bus/ Page Protection Mode | |
| Fabricantes | Siemens Semiconductor Group | |
| Logotipo |  |
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Standard EEPROM ICs
SLx 24C04/P
4 Kbit (512 × 8 bit)
Serial CMOS-EEPROM with
I2C Synchronous 2-Wire Bus
and Page Protection Mode™
Data Sheet 1998-07-27
1 page  
SLx 24C04/P
Pin Description
Serial Clock (SCL)
The SCL input is used to clock data into the device on the rising edge and to clock data
out of the device on the falling edge.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses, data or control information into the
device or to transfer data out of the device. The output is open drain, performing a wired
AND function with any number of other open drain or open collector devices. The SDA
bus requires a pull-up resistor to VCC.
Write Protection (WP)
WP switched to VSS allows normal read/write operations.
WP switched to VCC protects the entire EEPROM against changes (hardware write
protection).
Additionally write protection is managed by a protection bit associated to each page.
(refer to chapter 7 Page Protection ModeTM)
Semiconductor Group
5
1998-07-27
5 Page 
SLx 24C04/P
5 Write Operations
Changing of the EEPROM data is initiated by the master with the command byte CSW.
Depending on the state of the Write Protection pin WP and of the Protection Bits (refer
to chapter 7 Page Protection ModeTM) either one byte (Byte Write) or up to 16 bytes
(Page Write) are modified in one programming procedure.
5.1 Byte Write
Address Setting
Transmission of Data
Programming Cycle
After a START condition the master transmits the Chip Select
Write byte CSW. The EEPROM acknowledges the CSW byte
during the ninth clock cycle. The following byte with the
EEPROM address (A0 to A7) is loaded into the address
counter of the EEPROM and acknowledged by the EEPROM.
Finally the master transmits the data byte which is also
acknowledged by the EEPROM into the internal buffer.
Then the master applies a STOP condition which starts the
internal programming procedure. The data bytes are written in
the memory location addressed in the EEA byte (A0 to A7)
and the CSW byte (A8). The programming procedure consists
of an internally timed erase/write cycle. In the first step, the
selected byte is erased to “1”. With the next internal step, the
addressed byte is written according to the contents of the
buffer.
Bus Activity
Master
S
T
A Command Byte EEPROM Address
R CSW
EEA
T
Data Byte
S
T
O
P
SDA Line S
Bus Activity
EEPROM
0
A
C
K
P
AA
CC
KK
IED02129
Figure 7
Byte Write Sequence
The erase/write cycle is finished latest after 8 ms. Acknowledge polling may be used for
speed enhancement in order to indicate the end of the erase/write cycle (refer to
chapter 5.3 Acknowledge Polling).
Semiconductor Group
11
1998-07-27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet SLX24C04P.PDF ] | |
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